xref: /rk3399_ARM-atf/plat/arm/board/juno/juno_bl1_setup.c (revision 4da6f6cde3c72bd9786fc20141848c770c84f784)
1436223deSYatharth Kochar /*
207570d59SYatharth Kochar  * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
3436223deSYatharth Kochar  *
482cb2c1aSdp-arm  * SPDX-License-Identifier: BSD-3-Clause
5436223deSYatharth Kochar  */
6436223deSYatharth Kochar 
7436223deSYatharth Kochar #include <bl_common.h>
8*4da6f6cdSSathees Balya #include <debug.h>
9436223deSYatharth Kochar #include <errno.h>
10436223deSYatharth Kochar #include <plat_arm.h>
114adb10c1SIsla Mitchell #include <platform.h>
12*4da6f6cdSSathees Balya #include <sds.h>
1307570d59SYatharth Kochar #include <sp805.h>
14436223deSYatharth Kochar #include <tbbr_img_def.h>
15436223deSYatharth Kochar #include <v2m_def.h>
16436223deSYatharth Kochar 
1707570d59SYatharth Kochar void juno_reset_to_aarch32_state(void);
1807570d59SYatharth Kochar 
19*4da6f6cdSSathees Balya static int is_watchdog_reset(void)
20*4da6f6cdSSathees Balya {
21*4da6f6cdSSathees Balya #if !CSS_USE_SCMI_SDS_DRIVER
22*4da6f6cdSSathees Balya 	#define RESET_REASON_WDOG_RESET		(0x2)
23*4da6f6cdSSathees Balya 	const uint32_t *reset_flags_ptr = (const uint32_t *)SSC_GPRETN;
24*4da6f6cdSSathees Balya 
25*4da6f6cdSSathees Balya 	if ((*reset_flags_ptr & RESET_REASON_WDOG_RESET) != 0)
26*4da6f6cdSSathees Balya 		return 1;
27*4da6f6cdSSathees Balya 
28*4da6f6cdSSathees Balya 	return 0;
29*4da6f6cdSSathees Balya #else
30*4da6f6cdSSathees Balya 	int ret;
31*4da6f6cdSSathees Balya 	uint32_t scp_reset_synd_flags;
32*4da6f6cdSSathees Balya 
33*4da6f6cdSSathees Balya 	ret = sds_init();
34*4da6f6cdSSathees Balya 	if (ret != SDS_OK) {
35*4da6f6cdSSathees Balya 		ERROR("SCP SDS initialization failed\n");
36*4da6f6cdSSathees Balya 		panic();
37*4da6f6cdSSathees Balya 	}
38*4da6f6cdSSathees Balya 
39*4da6f6cdSSathees Balya 	ret = sds_struct_read(SDS_RESET_SYNDROME_STRUCT_ID,
40*4da6f6cdSSathees Balya 					SDS_RESET_SYNDROME_OFFSET,
41*4da6f6cdSSathees Balya 					&scp_reset_synd_flags,
42*4da6f6cdSSathees Balya 					SDS_RESET_SYNDROME_SIZE,
43*4da6f6cdSSathees Balya 					SDS_ACCESS_MODE_NON_CACHED);
44*4da6f6cdSSathees Balya 	if (ret != SDS_OK) {
45*4da6f6cdSSathees Balya 		ERROR("Getting reset reason from SDS failed\n");
46*4da6f6cdSSathees Balya 		panic();
47*4da6f6cdSSathees Balya 	}
48*4da6f6cdSSathees Balya 
49*4da6f6cdSSathees Balya 	/* Check if the WATCHDOG_RESET_BIT is set in the reset syndrome */
50*4da6f6cdSSathees Balya 	if (scp_reset_synd_flags & SDS_RESET_SYNDROME_AP_WD_RESET_BIT)
51*4da6f6cdSSathees Balya 		return 1;
52*4da6f6cdSSathees Balya 
53*4da6f6cdSSathees Balya 	return 0;
54*4da6f6cdSSathees Balya #endif
55*4da6f6cdSSathees Balya }
56*4da6f6cdSSathees Balya 
57*4da6f6cdSSathees Balya /*******************************************************************************
58*4da6f6cdSSathees Balya  * The following function checks if Firmware update is needed,
59*4da6f6cdSSathees Balya  * by checking if TOC in FIP image is valid or watchdog reset happened.
60*4da6f6cdSSathees Balya  ******************************************************************************/
61*4da6f6cdSSathees Balya int plat_arm_bl1_fwu_needed(void)
62*4da6f6cdSSathees Balya {
63*4da6f6cdSSathees Balya 	const uint32_t *nv_flags_ptr = (const uint32_t *)V2M_SYS_NVFLAGS_ADDR;
64*4da6f6cdSSathees Balya 
65*4da6f6cdSSathees Balya 	/* Check if TOC is invalid or watchdog reset happened. */
66*4da6f6cdSSathees Balya 	if ((arm_io_is_toc_valid() != 1) ||
67*4da6f6cdSSathees Balya 		(((*nv_flags_ptr == -EAUTH) || (*nv_flags_ptr == -ENOENT))
68*4da6f6cdSSathees Balya 		&& is_watchdog_reset()))
69*4da6f6cdSSathees Balya 		return 1;
70*4da6f6cdSSathees Balya 
71*4da6f6cdSSathees Balya 	return 0;
72*4da6f6cdSSathees Balya }
73*4da6f6cdSSathees Balya 
74436223deSYatharth Kochar /*******************************************************************************
75436223deSYatharth Kochar  * On JUNO update the arg2 with address of SCP_BL2U image info.
76436223deSYatharth Kochar  ******************************************************************************/
77436223deSYatharth Kochar void bl1_plat_set_ep_info(unsigned int image_id,
78436223deSYatharth Kochar 		entry_point_info_t *ep_info)
79436223deSYatharth Kochar {
80436223deSYatharth Kochar 	if (image_id == BL2U_IMAGE_ID) {
81436223deSYatharth Kochar 		image_desc_t *image_desc = bl1_plat_get_image_desc(SCP_BL2U_IMAGE_ID);
82436223deSYatharth Kochar 		ep_info->args.arg2 = (unsigned long)&image_desc->image_info;
83436223deSYatharth Kochar 	}
84436223deSYatharth Kochar }
85436223deSYatharth Kochar 
86436223deSYatharth Kochar /*******************************************************************************
87436223deSYatharth Kochar  * On Juno clear SYS_NVFLAGS and wait for watchdog reset.
88436223deSYatharth Kochar  ******************************************************************************/
891f37b944SDan Handley __dead2 void bl1_plat_fwu_done(void *client_cookie, void *reserved)
90436223deSYatharth Kochar {
91436223deSYatharth Kochar 	unsigned int *nv_flags_clr = (unsigned int *)
92436223deSYatharth Kochar 			(V2M_SYSREGS_BASE + V2M_SYS_NVFLAGSCLR);
93436223deSYatharth Kochar 	unsigned int *nv_flags_ptr = (unsigned int *)
94436223deSYatharth Kochar 			(V2M_SYSREGS_BASE + V2M_SYS_NVFLAGS);
95436223deSYatharth Kochar 
96436223deSYatharth Kochar 	/* Clear the NV flags register. */
97436223deSYatharth Kochar 	*nv_flags_clr = *nv_flags_ptr;
98436223deSYatharth Kochar 
99436223deSYatharth Kochar 	while (1)
100436223deSYatharth Kochar 		wfi();
101436223deSYatharth Kochar }
10207570d59SYatharth Kochar 
10307570d59SYatharth Kochar #if JUNO_AARCH32_EL3_RUNTIME
10407570d59SYatharth Kochar void bl1_plat_prepare_exit(entry_point_info_t *ep_info)
10507570d59SYatharth Kochar {
10607570d59SYatharth Kochar #if !ARM_DISABLE_TRUSTED_WDOG
10707570d59SYatharth Kochar 	/* Disable watchdog before leaving BL1 */
10807570d59SYatharth Kochar 	sp805_stop(ARM_SP805_TWDG_BASE);
10907570d59SYatharth Kochar #endif
11007570d59SYatharth Kochar 
11107570d59SYatharth Kochar 	juno_reset_to_aarch32_state();
11207570d59SYatharth Kochar }
11307570d59SYatharth Kochar #endif /* JUNO_AARCH32_EL3_RUNTIME */
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