1 /* 2 * Copyright (c) 2014-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <drivers/arm/tzc400.h> 11 #if TRUSTED_BOARD_BOOT 12 #include MBEDTLS_CONFIG_FILE 13 #endif 14 #include <plat/arm/board/common/board_css_def.h> 15 #include <plat/arm/board/common/v2m_def.h> 16 #include <plat/arm/common/arm_def.h> 17 #include <plat/arm/common/arm_spm_def.h> 18 #include <plat/arm/css/common/css_def.h> 19 #include <plat/arm/soc/common/soc_css_def.h> 20 #include <plat/common/common_def.h> 21 22 #include "../juno_def.h" 23 #ifdef JUNO_ETHOSN_TZMP1 24 #include "../juno_ethosn_tzmp1_def.h" 25 #endif 26 27 /* Required platform porting definitions */ 28 /* Juno supports system power domain */ 29 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL2 30 #define PLAT_NUM_PWR_DOMAINS (ARM_SYSTEM_COUNT + \ 31 JUNO_CLUSTER_COUNT + \ 32 PLATFORM_CORE_COUNT) 33 #define PLATFORM_CORE_COUNT (JUNO_CLUSTER0_CORE_COUNT + \ 34 JUNO_CLUSTER1_CORE_COUNT) 35 36 /* 37 * Other platform porting definitions are provided by included headers 38 */ 39 40 /* Define memory configuration for device tree files. */ 41 #define PLAT_ARM_HW_CONFIG_SIZE U(0x8000) 42 43 /* 44 * Required ARM standard platform porting definitions 45 */ 46 #define PLAT_ARM_CLUSTER_COUNT JUNO_CLUSTER_COUNT 47 48 #define PLAT_ARM_TRUSTED_SRAM_SIZE UL(0x00040000) /* 256 KB */ 49 50 /* Use the bypass address */ 51 #define PLAT_ARM_TRUSTED_ROM_BASE (V2M_FLASH0_BASE + \ 52 BL1_ROM_BYPASS_OFFSET) 53 54 #define NSRAM_BASE UL(0x2e000000) 55 #define NSRAM_SIZE UL(0x00008000) /* 32KB */ 56 57 #define PLAT_ARM_DRAM2_BASE ULL(0x880000000) 58 #define PLAT_ARM_DRAM2_SIZE ULL(0x180000000) 59 60 /* Range of kernel DTB load address */ 61 #define JUNO_DTB_DRAM_MAP_START ULL(0x82000000) 62 #define JUNO_DTB_DRAM_MAP_SIZE ULL(0x00008000) /* 32KB */ 63 64 #define ARM_DTB_DRAM_NS MAP_REGION_FLAT( \ 65 JUNO_DTB_DRAM_MAP_START, \ 66 JUNO_DTB_DRAM_MAP_SIZE, \ 67 MT_MEMORY | MT_RO | MT_NS) 68 69 #ifdef JUNO_ETHOSN_TZMP1 70 #define JUNO_ETHOSN_PROT_FW_RO MAP_REGION_FLAT( \ 71 JUNO_ETHOSN_FW_TZC_PROT_DRAM2_BASE, \ 72 JUNO_ETHOSN_FW_TZC_PROT_DRAM2_SIZE, \ 73 MT_RO_DATA | MT_SECURE) 74 75 #define JUNO_ETHOSN_PROT_FW_RW MAP_REGION_FLAT( \ 76 JUNO_ETHOSN_FW_TZC_PROT_DRAM2_BASE, \ 77 JUNO_ETHOSN_FW_TZC_PROT_DRAM2_SIZE, \ 78 MT_MEMORY | MT_RW | MT_SECURE) 79 #endif 80 81 /* virtual address used by dynamic mem_protect for chunk_base */ 82 #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000) 83 84 /* 85 * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page 86 */ 87 88 #if USE_ROMLIB 89 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0x1000) 90 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0xe000) 91 #define JUNO_BL2_ROMLIB_OPTIMIZATION UL(0x8000) 92 #else 93 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0) 94 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0) 95 #define JUNO_BL2_ROMLIB_OPTIMIZATION UL(0) 96 #endif 97 98 /* 99 * Actual ROM size on Juno is 64 KB, but TBB currently requires at least 80 KB 100 * in debug mode. We can test TBB on Juno bypassing the ROM and using 128 KB of 101 * flash 102 */ 103 104 #if TRUSTED_BOARD_BOOT 105 #define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x00020000) 106 #else 107 #define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x00010000) 108 #endif /* TRUSTED_BOARD_BOOT */ 109 110 /* 111 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the 112 * plat_arm_mmap array defined for each BL stage. 113 */ 114 #ifdef IMAGE_BL1 115 # define PLAT_ARM_MMAP_ENTRIES 7 116 # define MAX_XLAT_TABLES 4 117 #endif 118 119 #ifdef IMAGE_BL2 120 #ifdef SPD_opteed 121 # define PLAT_ARM_MMAP_ENTRIES 13 122 # define MAX_XLAT_TABLES 5 123 #else 124 # define PLAT_ARM_MMAP_ENTRIES 11 125 # define MAX_XLAT_TABLES 5 126 #endif 127 #endif 128 129 #ifdef IMAGE_BL2U 130 # define PLAT_ARM_MMAP_ENTRIES 5 131 # define MAX_XLAT_TABLES 3 132 #endif 133 134 #ifdef IMAGE_BL31 135 # if SPMC_AT_EL3 136 # define PLAT_ARM_MMAP_ENTRIES 10 137 # define MAX_XLAT_TABLES 8 138 # define PLAT_SP_IMAGE_MMAP_REGIONS 30 139 # define PLAT_SP_IMAGE_MAX_XLAT_TABLES 12 140 # else 141 # define PLAT_ARM_MMAP_ENTRIES 8 142 # define MAX_XLAT_TABLES 6 143 # endif 144 #endif 145 146 #ifdef IMAGE_BL32 147 # define PLAT_ARM_MMAP_ENTRIES 6 148 # define MAX_XLAT_TABLES 4 149 #endif 150 151 #if SPMC_AT_EL3 152 /* 153 * Number of Secure Partitions supported. 154 * SPMC at EL3, uses this count to configure the maximum number of supported 155 * secure partitions. 156 */ 157 #define SECURE_PARTITION_COUNT 1 158 159 /* 160 * Number of Normal World Partitions supported. 161 * SPMC at EL3, uses this count to configure the maximum number of supported 162 * NWd partitions. 163 */ 164 #define NS_PARTITION_COUNT 1 165 166 /* 167 * Number of Logical Partitions supported. 168 * SPMC at EL3, uses this count to configure the maximum number of supported 169 * logical partitions. 170 */ 171 #define MAX_EL3_LP_DESCS_COUNT 1 172 173 #endif /* SPMC_AT_EL3 */ 174 175 /* 176 * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size 177 * plus a little space for growth. 178 */ 179 #if TRUSTED_BOARD_BOOT 180 # define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xB000) 181 #else 182 # define PLAT_ARM_MAX_BL1_RW_SIZE UL(0x6000) 183 #endif 184 185 /* 186 * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a 187 * little space for growth. 188 */ 189 #if TRUSTED_BOARD_BOOT 190 #if TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA 191 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x20000) - JUNO_BL2_ROMLIB_OPTIMIZATION) 192 #elif TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_ECDSA 193 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1D000) - JUNO_BL2_ROMLIB_OPTIMIZATION) 194 #else 195 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1D000) - JUNO_BL2_ROMLIB_OPTIMIZATION) 196 #endif 197 #else 198 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x13000) - JUNO_BL2_ROMLIB_OPTIMIZATION) 199 #endif 200 201 /* 202 * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is 203 * calculated using the current BL31 PROGBITS debug size plus the sizes of 204 * BL2 and BL1-RW. SCP_BL2 image is loaded into the space BL31 -> BL2_BASE. 205 * Hence the BL31 PROGBITS size should be >= PLAT_CSS_MAX_SCP_BL2_SIZE. 206 */ 207 #define PLAT_ARM_MAX_BL31_SIZE UL(0x3D000) 208 209 #if JUNO_AARCH32_EL3_RUNTIME 210 /* 211 * Since BL32 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL32_SIZE is 212 * calculated using the current BL32 PROGBITS debug size plus the sizes of 213 * BL2 and BL1-RW. SCP_BL2 image is loaded into the space BL32 -> BL2_BASE. 214 * Hence the BL32 PROGBITS size should be >= PLAT_CSS_MAX_SCP_BL2_SIZE. 215 */ 216 #define PLAT_ARM_MAX_BL32_SIZE UL(0x3D000) 217 #endif 218 219 /* 220 * Size of cacheable stacks 221 */ 222 #if defined(IMAGE_BL1) 223 # if TRUSTED_BOARD_BOOT 224 # define PLATFORM_STACK_SIZE UL(0x1000) 225 # else 226 # define PLATFORM_STACK_SIZE UL(0x440) 227 # endif 228 #elif defined(IMAGE_BL2) 229 # if TRUSTED_BOARD_BOOT 230 # define PLATFORM_STACK_SIZE UL(0x1000) 231 # else 232 # define PLATFORM_STACK_SIZE UL(0x400) 233 # endif 234 #elif defined(IMAGE_BL2U) 235 # define PLATFORM_STACK_SIZE UL(0x400) 236 #elif defined(IMAGE_BL31) 237 # if PLAT_XLAT_TABLES_DYNAMIC 238 # define PLATFORM_STACK_SIZE UL(0x800) 239 # else 240 # define PLATFORM_STACK_SIZE UL(0x400) 241 # endif 242 #elif defined(IMAGE_BL32) 243 # define PLATFORM_STACK_SIZE UL(0x440) 244 #endif 245 246 #define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \ 247 PLAT_SP_IMAGE_NS_BUF_SIZE) 248 249 /* CCI related constants */ 250 #define PLAT_ARM_CCI_BASE UL(0x2c090000) 251 #define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 4 252 #define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 3 253 254 /* System timer related constants */ 255 #define PLAT_ARM_NSTIMER_FRAME_ID U(1) 256 257 /* TZC related constants */ 258 #define PLAT_ARM_TZC_BASE UL(0x2a4a0000) 259 #define PLAT_ARM_TZC_NS_DEV_ACCESS ( \ 260 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CCI400) | \ 261 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_PCIE) | \ 262 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD0) | \ 263 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD1) | \ 264 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_USB) | \ 265 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_DMA330) | \ 266 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_THINLINKS) | \ 267 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_AP) | \ 268 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_GPU) | \ 269 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CORESIGHT)) 270 271 /* TZC related constants */ 272 #define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT_ALL 273 274 /* 275 * Required ARM CSS based platform porting definitions 276 */ 277 278 /* GIC related constants (no GICR in GIC-400) */ 279 #define PLAT_ARM_GICD_BASE UL(0x2c010000) 280 #define PLAT_ARM_GICC_BASE UL(0x2c02f000) 281 #define PLAT_ARM_GICH_BASE UL(0x2c04f000) 282 #define PLAT_ARM_GICV_BASE UL(0x2c06f000) 283 284 /* MHU related constants */ 285 #define PLAT_CSS_MHU_BASE UL(0x2b1f0000) 286 287 #if CSS_USE_SCMI_SDS_DRIVER 288 /* Index of SDS region used in the communication between AP and SCP */ 289 #define SDS_SCP_AP_REGION_ID U(0) 290 #else 291 /* 292 * Base address of the first memory region used for communication between AP 293 * and SCP. Used by the BOM and SCPI protocols. 294 * 295 * Note that this is located at the same address as SCP_BOOT_CFG_ADDR, which 296 * means the SCP/AP configuration data gets overwritten when the AP initiates 297 * communication with the SCP. The configuration data is expected to be a 298 * 32-bit word on all CSS platforms. On Juno, part of this configuration is 299 * which CPU is the primary, according to the shift and mask definitions below. 300 */ 301 #define PLAT_CSS_SCP_COM_SHARED_MEM_BASE (ARM_TRUSTED_SRAM_BASE + UL(0x80)) 302 #define PLAT_CSS_PRIMARY_CPU_SHIFT 8 303 #define PLAT_CSS_PRIMARY_CPU_BIT_WIDTH 4 304 #endif /* CSS_USE_SCMI_SDS_DRIVER */ 305 306 /* 307 * SCP_BL2 uses up whatever remaining space is available as it is loaded before 308 * anything else in this memory region and is handed over to the SCP before 309 * BL31 is loaded over the top. 310 */ 311 #define PLAT_CSS_MAX_SCP_BL2_SIZE \ 312 ((SCP_BL2_LIMIT - ARM_FW_CONFIG_LIMIT) & ~PAGE_SIZE_MASK) 313 314 #define PLAT_CSS_MAX_SCP_BL2U_SIZE PLAT_CSS_MAX_SCP_BL2_SIZE 315 316 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 317 CSS_G1S_IRQ_PROPS(grp), \ 318 ARM_G1S_IRQ_PROPS(grp), \ 319 INTR_PROP_DESC(JUNO_IRQ_DMA_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 320 (grp), GIC_INTR_CFG_LEVEL), \ 321 INTR_PROP_DESC(JUNO_IRQ_HDLCD0_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 322 (grp), GIC_INTR_CFG_LEVEL), \ 323 INTR_PROP_DESC(JUNO_IRQ_HDLCD1_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 324 (grp), GIC_INTR_CFG_LEVEL), \ 325 INTR_PROP_DESC(JUNO_IRQ_USB_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 326 (grp), GIC_INTR_CFG_LEVEL), \ 327 INTR_PROP_DESC(JUNO_IRQ_THIN_LINKS_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 328 (grp), GIC_INTR_CFG_LEVEL), \ 329 INTR_PROP_DESC(JUNO_IRQ_SEC_I2C, GIC_HIGHEST_SEC_PRIORITY, \ 330 (grp), GIC_INTR_CFG_LEVEL), \ 331 INTR_PROP_DESC(JUNO_IRQ_GPU_SMMU_1, GIC_HIGHEST_SEC_PRIORITY, \ 332 (grp), GIC_INTR_CFG_LEVEL), \ 333 INTR_PROP_DESC(JUNO_IRQ_ETR_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 334 (grp), GIC_INTR_CFG_LEVEL) 335 336 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) 337 338 /* 339 * Required ARM CSS SoC based platform porting definitions 340 */ 341 342 /* CSS SoC NIC-400 Global Programmers View (GPV) */ 343 #define PLAT_SOC_CSS_NIC400_BASE UL(0x2a000000) 344 345 #define PLAT_ARM_PRIVATE_SDEI_EVENTS ARM_SDEI_PRIVATE_EVENTS 346 #define PLAT_ARM_SHARED_SDEI_EVENTS ARM_SDEI_SHARED_EVENTS 347 348 /* System power domain level */ 349 #define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2 350 351 /* 352 * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes 353 */ 354 #ifdef __aarch64__ 355 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) 356 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) 357 #else 358 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 359 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 360 #endif 361 362 /* Number of SCMI channels on the platform */ 363 #define PLAT_ARM_SCMI_CHANNEL_COUNT U(1) 364 365 /* Protected NSAIDs and memory regions for the Arm(R) Ethos(TM)-N NPU driver */ 366 #ifdef JUNO_ETHOSN_TZMP1 367 #define ETHOSN_NPU_PROT_FW_NSAID JUNO_ETHOSN_TZC400_NSAID_FW_PROT 368 #define ETHOSN_NPU_PROT_RW_DATA_NSAID JUNO_ETHOSN_TZC400_NSAID_DATA_RW_PROT 369 #define ETHOSN_NPU_PROT_RO_DATA_NSAID JUNO_ETHOSN_TZC400_NSAID_DATA_RO_PROT 370 371 #define ETHOSN_NPU_NS_RW_DATA_NSAID JUNO_ETHOSN_TZC400_NSAID_DATA_RW_NS 372 #define ETHOSN_NPU_NS_RO_DATA_NSAID JUNO_ETHOSN_TZC400_NSAID_DATA_RO_NS 373 374 #define ETHOSN_NPU_FW_IMAGE_BASE JUNO_ETHOSN_FW_TZC_PROT_DRAM2_BASE 375 #define ETHOSN_NPU_FW_IMAGE_LIMIT \ 376 (JUNO_ETHOSN_FW_TZC_PROT_DRAM2_BASE + JUNO_ETHOSN_FW_TZC_PROT_DRAM2_SIZE) 377 #endif 378 379 #endif /* PLATFORM_DEF_H */ 380