1 /* 2 * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <drivers/arm/tzc400.h> 11 #if TRUSTED_BOARD_BOOT 12 #include <drivers/auth/mbedtls/mbedtls_config.h> 13 #endif 14 #include <plat/arm/board/common/board_css_def.h> 15 #include <plat/arm/board/common/v2m_def.h> 16 #include <plat/arm/common/arm_def.h> 17 #include <plat/arm/css/common/css_def.h> 18 #include <plat/arm/soc/common/soc_css_def.h> 19 #include <plat/common/common_def.h> 20 21 #include "../juno_def.h" 22 23 /* Required platform porting definitions */ 24 /* Juno supports system power domain */ 25 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL2 26 #define PLAT_NUM_PWR_DOMAINS (ARM_SYSTEM_COUNT + \ 27 JUNO_CLUSTER_COUNT + \ 28 PLATFORM_CORE_COUNT) 29 #define PLATFORM_CORE_COUNT (JUNO_CLUSTER0_CORE_COUNT + \ 30 JUNO_CLUSTER1_CORE_COUNT) 31 32 /* Cryptocell HW Base address */ 33 #define PLAT_CRYPTOCELL_BASE UL(0x60050000) 34 35 /* 36 * Other platform porting definitions are provided by included headers 37 */ 38 39 /* 40 * Required ARM standard platform porting definitions 41 */ 42 #define PLAT_ARM_CLUSTER_COUNT JUNO_CLUSTER_COUNT 43 44 #define PLAT_ARM_TRUSTED_SRAM_SIZE UL(0x00040000) /* 256 KB */ 45 46 /* Use the bypass address */ 47 #define PLAT_ARM_TRUSTED_ROM_BASE (V2M_FLASH0_BASE + \ 48 BL1_ROM_BYPASS_OFFSET) 49 50 #define NSRAM_BASE UL(0x2e000000) 51 #define NSRAM_SIZE UL(0x00008000) /* 32KB */ 52 53 /* virtual address used by dynamic mem_protect for chunk_base */ 54 #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000) 55 56 /* 57 * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page 58 */ 59 60 #if USE_ROMLIB 61 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0x1000) 62 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0xe000) 63 #else 64 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0) 65 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0) 66 #endif 67 68 /* 69 * Actual ROM size on Juno is 64 KB, but TBB currently requires at least 80 KB 70 * in debug mode. We can test TBB on Juno bypassing the ROM and using 128 KB of 71 * flash 72 */ 73 74 #if TRUSTED_BOARD_BOOT 75 #define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x00020000) 76 #else 77 #define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x00010000) 78 #endif /* TRUSTED_BOARD_BOOT */ 79 80 /* 81 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the 82 * plat_arm_mmap array defined for each BL stage. 83 */ 84 #ifdef IMAGE_BL1 85 # define PLAT_ARM_MMAP_ENTRIES 7 86 # define MAX_XLAT_TABLES 4 87 #endif 88 89 #ifdef IMAGE_BL2 90 #ifdef SPD_opteed 91 # define PLAT_ARM_MMAP_ENTRIES 11 92 # define MAX_XLAT_TABLES 5 93 #else 94 # define PLAT_ARM_MMAP_ENTRIES 10 95 # define MAX_XLAT_TABLES 4 96 #endif 97 #endif 98 99 #ifdef IMAGE_BL2U 100 # define PLAT_ARM_MMAP_ENTRIES 5 101 # define MAX_XLAT_TABLES 3 102 #endif 103 104 #ifdef IMAGE_BL31 105 # define PLAT_ARM_MMAP_ENTRIES 7 106 # define MAX_XLAT_TABLES 3 107 #endif 108 109 #ifdef IMAGE_BL32 110 # define PLAT_ARM_MMAP_ENTRIES 6 111 # define MAX_XLAT_TABLES 4 112 #endif 113 114 /* 115 * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size 116 * plus a little space for growth. 117 */ 118 #if TRUSTED_BOARD_BOOT 119 # define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xB000) 120 #else 121 # define PLAT_ARM_MAX_BL1_RW_SIZE UL(0x6000) 122 #endif 123 124 /* 125 * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a 126 * little space for growth. 127 */ 128 #if TRUSTED_BOARD_BOOT 129 #if TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA 130 # define PLAT_ARM_MAX_BL2_SIZE UL(0x1F000) 131 #elif TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_ECDSA 132 # define PLAT_ARM_MAX_BL2_SIZE UL(0x1D000) 133 #else 134 # define PLAT_ARM_MAX_BL2_SIZE UL(0x1D000) 135 #endif 136 #else 137 # define PLAT_ARM_MAX_BL2_SIZE UL(0xF000) 138 #endif 139 140 /* 141 * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is 142 * calculated using the current BL31 PROGBITS debug size plus the sizes of 143 * BL2 and BL1-RW. SCP_BL2 image is loaded into the space BL31 -> BL2_BASE. 144 * Hence the BL31 PROGBITS size should be >= PLAT_CSS_MAX_SCP_BL2_SIZE. 145 */ 146 #define PLAT_ARM_MAX_BL31_SIZE UL(0x3E000) 147 148 #if JUNO_AARCH32_EL3_RUNTIME 149 /* 150 * Since BL32 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL32_SIZE is 151 * calculated using the current BL32 PROGBITS debug size plus the sizes of 152 * BL2 and BL1-RW. SCP_BL2 image is loaded into the space BL32 -> BL2_BASE. 153 * Hence the BL32 PROGBITS size should be >= PLAT_CSS_MAX_SCP_BL2_SIZE. 154 */ 155 #define PLAT_ARM_MAX_BL32_SIZE UL(0x3E000) 156 #endif 157 158 /* 159 * Size of cacheable stacks 160 */ 161 #if defined(IMAGE_BL1) 162 # if TRUSTED_BOARD_BOOT 163 # define PLATFORM_STACK_SIZE UL(0x1000) 164 # else 165 # define PLATFORM_STACK_SIZE UL(0x440) 166 # endif 167 #elif defined(IMAGE_BL2) 168 # if TRUSTED_BOARD_BOOT 169 # define PLATFORM_STACK_SIZE UL(0x1000) 170 # else 171 # define PLATFORM_STACK_SIZE UL(0x400) 172 # endif 173 #elif defined(IMAGE_BL2U) 174 # define PLATFORM_STACK_SIZE UL(0x400) 175 #elif defined(IMAGE_BL31) 176 # if PLAT_XLAT_TABLES_DYNAMIC 177 # define PLATFORM_STACK_SIZE UL(0x800) 178 # else 179 # define PLATFORM_STACK_SIZE UL(0x400) 180 # endif 181 #elif defined(IMAGE_BL32) 182 # define PLATFORM_STACK_SIZE UL(0x440) 183 #endif 184 185 /* 186 * Since free SRAM space is scant, enable the ASSERTION message size 187 * optimization by fixing the PLAT_LOG_LEVEL_ASSERT to LOG_LEVEL_INFO (40). 188 */ 189 #define PLAT_LOG_LEVEL_ASSERT 40 190 191 /* CCI related constants */ 192 #define PLAT_ARM_CCI_BASE UL(0x2c090000) 193 #define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 4 194 #define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 3 195 196 /* System timer related constants */ 197 #define PLAT_ARM_NSTIMER_FRAME_ID U(1) 198 199 /* TZC related constants */ 200 #define PLAT_ARM_TZC_BASE UL(0x2a4a0000) 201 #define PLAT_ARM_TZC_NS_DEV_ACCESS ( \ 202 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CCI400) | \ 203 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_PCIE) | \ 204 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD0) | \ 205 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD1) | \ 206 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_USB) | \ 207 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_DMA330) | \ 208 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_THINLINKS) | \ 209 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_AP) | \ 210 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_GPU) | \ 211 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CORESIGHT)) 212 213 /* 214 * Required ARM CSS based platform porting definitions 215 */ 216 217 /* GIC related constants (no GICR in GIC-400) */ 218 #define PLAT_ARM_GICD_BASE UL(0x2c010000) 219 #define PLAT_ARM_GICC_BASE UL(0x2c02f000) 220 #define PLAT_ARM_GICH_BASE UL(0x2c04f000) 221 #define PLAT_ARM_GICV_BASE UL(0x2c06f000) 222 223 /* MHU related constants */ 224 #define PLAT_CSS_MHU_BASE UL(0x2b1f0000) 225 #define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE 226 227 /* 228 * Base address of the first memory region used for communication between AP 229 * and SCP. Used by the BOM and SCPI protocols. 230 */ 231 #if !CSS_USE_SCMI_SDS_DRIVER 232 /* 233 * Note that this is located at the same address as SCP_BOOT_CFG_ADDR, which 234 * means the SCP/AP configuration data gets overwritten when the AP initiates 235 * communication with the SCP. The configuration data is expected to be a 236 * 32-bit word on all CSS platforms. On Juno, part of this configuration is 237 * which CPU is the primary, according to the shift and mask definitions below. 238 */ 239 #define PLAT_CSS_SCP_COM_SHARED_MEM_BASE (ARM_TRUSTED_SRAM_BASE + UL(0x80)) 240 #define PLAT_CSS_PRIMARY_CPU_SHIFT 8 241 #define PLAT_CSS_PRIMARY_CPU_BIT_WIDTH 4 242 #endif 243 244 /* 245 * PLAT_CSS_MAX_SCP_BL2_SIZE is calculated using the current 246 * SCP_BL2 size plus a little space for growth. 247 */ 248 #define PLAT_CSS_MAX_SCP_BL2_SIZE UL(0x14000) 249 250 /* 251 * PLAT_CSS_MAX_SCP_BL2U_SIZE is calculated using the current 252 * SCP_BL2U size plus a little space for growth. 253 */ 254 #define PLAT_CSS_MAX_SCP_BL2U_SIZE UL(0x14000) 255 256 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 257 CSS_G1S_IRQ_PROPS(grp), \ 258 ARM_G1S_IRQ_PROPS(grp), \ 259 INTR_PROP_DESC(JUNO_IRQ_DMA_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 260 (grp), GIC_INTR_CFG_LEVEL), \ 261 INTR_PROP_DESC(JUNO_IRQ_HDLCD0_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 262 (grp), GIC_INTR_CFG_LEVEL), \ 263 INTR_PROP_DESC(JUNO_IRQ_HDLCD1_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 264 (grp), GIC_INTR_CFG_LEVEL), \ 265 INTR_PROP_DESC(JUNO_IRQ_USB_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 266 (grp), GIC_INTR_CFG_LEVEL), \ 267 INTR_PROP_DESC(JUNO_IRQ_THIN_LINKS_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 268 (grp), GIC_INTR_CFG_LEVEL), \ 269 INTR_PROP_DESC(JUNO_IRQ_SEC_I2C, GIC_HIGHEST_SEC_PRIORITY, \ 270 (grp), GIC_INTR_CFG_LEVEL), \ 271 INTR_PROP_DESC(JUNO_IRQ_GPU_SMMU_1, GIC_HIGHEST_SEC_PRIORITY, \ 272 (grp), GIC_INTR_CFG_LEVEL), \ 273 INTR_PROP_DESC(JUNO_IRQ_ETR_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 274 (grp), GIC_INTR_CFG_LEVEL) 275 276 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) 277 278 /* 279 * Required ARM CSS SoC based platform porting definitions 280 */ 281 282 /* CSS SoC NIC-400 Global Programmers View (GPV) */ 283 #define PLAT_SOC_CSS_NIC400_BASE UL(0x2a000000) 284 285 #define PLAT_ARM_PRIVATE_SDEI_EVENTS ARM_SDEI_PRIVATE_EVENTS 286 #define PLAT_ARM_SHARED_SDEI_EVENTS ARM_SDEI_SHARED_EVENTS 287 288 /* System power domain level */ 289 #define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2 290 291 /* 292 * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes 293 */ 294 #ifdef __aarch64__ 295 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) 296 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) 297 #else 298 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 299 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 300 #endif 301 302 #endif /* PLATFORM_DEF_H */ 303