1 /* 2 * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 /* Enable the dynamic translation tables library. */ 11 #ifdef AARCH32 12 # if defined(IMAGE_BL32) && RESET_TO_SP_MIN 13 # define PLAT_XLAT_TABLES_DYNAMIC 1 14 # endif 15 #else 16 # if defined(IMAGE_BL31) && RESET_TO_BL31 17 # define PLAT_XLAT_TABLES_DYNAMIC 1 18 # endif 19 #endif /* AARCH32 */ 20 21 22 #include <drivers/arm/tzc400.h> 23 #if TRUSTED_BOARD_BOOT 24 #include <drivers/auth/mbedtls/mbedtls_config.h> 25 #endif 26 #include <plat/common/common_def.h> 27 28 #include <arm_def.h> 29 #include <board_css_def.h> 30 #include <css_def.h> 31 #include <soc_css_def.h> 32 #include <v2m_def.h> 33 #include "../juno_def.h" 34 35 /* Required platform porting definitions */ 36 /* Juno supports system power domain */ 37 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL2 38 #define PLAT_NUM_PWR_DOMAINS (ARM_SYSTEM_COUNT + \ 39 JUNO_CLUSTER_COUNT + \ 40 PLATFORM_CORE_COUNT) 41 #define PLATFORM_CORE_COUNT (JUNO_CLUSTER0_CORE_COUNT + \ 42 JUNO_CLUSTER1_CORE_COUNT) 43 44 /* Cryptocell HW Base address */ 45 #define PLAT_CRYPTOCELL_BASE UL(0x60050000) 46 47 /* 48 * Other platform porting definitions are provided by included headers 49 */ 50 51 /* 52 * Required ARM standard platform porting definitions 53 */ 54 #define PLAT_ARM_CLUSTER_COUNT JUNO_CLUSTER_COUNT 55 56 #define PLAT_ARM_TRUSTED_SRAM_SIZE UL(0x00040000) /* 256 KB */ 57 58 /* Use the bypass address */ 59 #define PLAT_ARM_TRUSTED_ROM_BASE (V2M_FLASH0_BASE + \ 60 BL1_ROM_BYPASS_OFFSET) 61 62 #define NSRAM_BASE UL(0x2e000000) 63 #define NSRAM_SIZE UL(0x00008000) /* 32KB */ 64 65 /* virtual address used by dynamic mem_protect for chunk_base */ 66 #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000) 67 68 /* 69 * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page 70 */ 71 72 #if USE_ROMLIB 73 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0x1000) 74 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0xe000) 75 #else 76 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0) 77 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0) 78 #endif 79 80 /* 81 * Actual ROM size on Juno is 64 KB, but TBB currently requires at least 80 KB 82 * in debug mode. We can test TBB on Juno bypassing the ROM and using 128 KB of 83 * flash 84 */ 85 86 #if TRUSTED_BOARD_BOOT 87 #define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x00020000) 88 #else 89 #define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x00010000) 90 #endif /* TRUSTED_BOARD_BOOT */ 91 92 /* 93 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the 94 * plat_arm_mmap array defined for each BL stage. 95 */ 96 #ifdef IMAGE_BL1 97 # define PLAT_ARM_MMAP_ENTRIES 7 98 # define MAX_XLAT_TABLES 4 99 #endif 100 101 #ifdef IMAGE_BL2 102 #ifdef SPD_opteed 103 # define PLAT_ARM_MMAP_ENTRIES 11 104 # define MAX_XLAT_TABLES 5 105 #else 106 # define PLAT_ARM_MMAP_ENTRIES 10 107 # define MAX_XLAT_TABLES 4 108 #endif 109 #endif 110 111 #ifdef IMAGE_BL2U 112 # define PLAT_ARM_MMAP_ENTRIES 5 113 # define MAX_XLAT_TABLES 3 114 #endif 115 116 #ifdef IMAGE_BL31 117 # define PLAT_ARM_MMAP_ENTRIES 7 118 # define MAX_XLAT_TABLES 3 119 #endif 120 121 #ifdef IMAGE_BL32 122 # define PLAT_ARM_MMAP_ENTRIES 6 123 # define MAX_XLAT_TABLES 4 124 #endif 125 126 /* 127 * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size 128 * plus a little space for growth. 129 */ 130 #if TRUSTED_BOARD_BOOT 131 # define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xB000) 132 #else 133 # define PLAT_ARM_MAX_BL1_RW_SIZE UL(0x6000) 134 #endif 135 136 /* 137 * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a 138 * little space for growth. 139 */ 140 #if TRUSTED_BOARD_BOOT 141 #if TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA 142 # define PLAT_ARM_MAX_BL2_SIZE UL(0x1F000) 143 #elif TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_ECDSA 144 # define PLAT_ARM_MAX_BL2_SIZE UL(0x1D000) 145 #else 146 # define PLAT_ARM_MAX_BL2_SIZE UL(0x1C000) 147 #endif 148 #else 149 # define PLAT_ARM_MAX_BL2_SIZE UL(0xF000) 150 #endif 151 152 /* 153 * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is 154 * calculated using the current BL31 PROGBITS debug size plus the sizes of 155 * BL2 and BL1-RW. SCP_BL2 image is loaded into the space BL31 -> BL2_BASE. 156 * Hence the BL31 PROGBITS size should be >= PLAT_CSS_MAX_SCP_BL2_SIZE. 157 */ 158 #define PLAT_ARM_MAX_BL31_SIZE UL(0x3E000) 159 160 #if JUNO_AARCH32_EL3_RUNTIME 161 /* 162 * Since BL32 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL32_SIZE is 163 * calculated using the current BL32 PROGBITS debug size plus the sizes of 164 * BL2 and BL1-RW. SCP_BL2 image is loaded into the space BL32 -> BL2_BASE. 165 * Hence the BL32 PROGBITS size should be >= PLAT_CSS_MAX_SCP_BL2_SIZE. 166 */ 167 #define PLAT_ARM_MAX_BL32_SIZE UL(0x3E000) 168 #endif 169 170 /* 171 * Size of cacheable stacks 172 */ 173 #if defined(IMAGE_BL1) 174 # if TRUSTED_BOARD_BOOT 175 # define PLATFORM_STACK_SIZE UL(0x1000) 176 # else 177 # define PLATFORM_STACK_SIZE UL(0x440) 178 # endif 179 #elif defined(IMAGE_BL2) 180 # if TRUSTED_BOARD_BOOT 181 # define PLATFORM_STACK_SIZE UL(0x1000) 182 # else 183 # define PLATFORM_STACK_SIZE UL(0x400) 184 # endif 185 #elif defined(IMAGE_BL2U) 186 # define PLATFORM_STACK_SIZE UL(0x400) 187 #elif defined(IMAGE_BL31) 188 # if PLAT_XLAT_TABLES_DYNAMIC 189 # define PLATFORM_STACK_SIZE UL(0x800) 190 # else 191 # define PLATFORM_STACK_SIZE UL(0x400) 192 # endif 193 #elif defined(IMAGE_BL32) 194 # define PLATFORM_STACK_SIZE UL(0x440) 195 #endif 196 197 /* 198 * Since free SRAM space is scant, enable the ASSERTION message size 199 * optimization by fixing the PLAT_LOG_LEVEL_ASSERT to LOG_LEVEL_INFO (40). 200 */ 201 #define PLAT_LOG_LEVEL_ASSERT 40 202 203 /* CCI related constants */ 204 #define PLAT_ARM_CCI_BASE UL(0x2c090000) 205 #define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 4 206 #define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 3 207 208 /* System timer related constants */ 209 #define PLAT_ARM_NSTIMER_FRAME_ID U(1) 210 211 /* TZC related constants */ 212 #define PLAT_ARM_TZC_BASE UL(0x2a4a0000) 213 #define PLAT_ARM_TZC_NS_DEV_ACCESS ( \ 214 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CCI400) | \ 215 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_PCIE) | \ 216 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD0) | \ 217 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD1) | \ 218 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_USB) | \ 219 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_DMA330) | \ 220 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_THINLINKS) | \ 221 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_AP) | \ 222 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_GPU) | \ 223 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CORESIGHT)) 224 225 /* 226 * Required ARM CSS based platform porting definitions 227 */ 228 229 /* GIC related constants (no GICR in GIC-400) */ 230 #define PLAT_ARM_GICD_BASE UL(0x2c010000) 231 #define PLAT_ARM_GICC_BASE UL(0x2c02f000) 232 #define PLAT_ARM_GICH_BASE UL(0x2c04f000) 233 #define PLAT_ARM_GICV_BASE UL(0x2c06f000) 234 235 /* MHU related constants */ 236 #define PLAT_CSS_MHU_BASE UL(0x2b1f0000) 237 238 /* 239 * Base address of the first memory region used for communication between AP 240 * and SCP. Used by the BOM and SCPI protocols. 241 */ 242 #if !CSS_USE_SCMI_SDS_DRIVER 243 /* 244 * Note that this is located at the same address as SCP_BOOT_CFG_ADDR, which 245 * means the SCP/AP configuration data gets overwritten when the AP initiates 246 * communication with the SCP. The configuration data is expected to be a 247 * 32-bit word on all CSS platforms. On Juno, part of this configuration is 248 * which CPU is the primary, according to the shift and mask definitions below. 249 */ 250 #define PLAT_CSS_SCP_COM_SHARED_MEM_BASE (ARM_TRUSTED_SRAM_BASE + UL(0x80)) 251 #define PLAT_CSS_PRIMARY_CPU_SHIFT 8 252 #define PLAT_CSS_PRIMARY_CPU_BIT_WIDTH 4 253 #endif 254 255 /* 256 * PLAT_CSS_MAX_SCP_BL2_SIZE is calculated using the current 257 * SCP_BL2 size plus a little space for growth. 258 */ 259 #define PLAT_CSS_MAX_SCP_BL2_SIZE UL(0x14000) 260 261 /* 262 * PLAT_CSS_MAX_SCP_BL2U_SIZE is calculated using the current 263 * SCP_BL2U size plus a little space for growth. 264 */ 265 #define PLAT_CSS_MAX_SCP_BL2U_SIZE UL(0x14000) 266 267 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 268 CSS_G1S_IRQ_PROPS(grp), \ 269 ARM_G1S_IRQ_PROPS(grp), \ 270 INTR_PROP_DESC(JUNO_IRQ_DMA_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 271 (grp), GIC_INTR_CFG_LEVEL), \ 272 INTR_PROP_DESC(JUNO_IRQ_HDLCD0_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 273 (grp), GIC_INTR_CFG_LEVEL), \ 274 INTR_PROP_DESC(JUNO_IRQ_HDLCD1_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 275 (grp), GIC_INTR_CFG_LEVEL), \ 276 INTR_PROP_DESC(JUNO_IRQ_USB_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 277 (grp), GIC_INTR_CFG_LEVEL), \ 278 INTR_PROP_DESC(JUNO_IRQ_THIN_LINKS_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 279 (grp), GIC_INTR_CFG_LEVEL), \ 280 INTR_PROP_DESC(JUNO_IRQ_SEC_I2C, GIC_HIGHEST_SEC_PRIORITY, \ 281 (grp), GIC_INTR_CFG_LEVEL), \ 282 INTR_PROP_DESC(JUNO_IRQ_GPU_SMMU_1, GIC_HIGHEST_SEC_PRIORITY, \ 283 (grp), GIC_INTR_CFG_LEVEL), \ 284 INTR_PROP_DESC(JUNO_IRQ_ETR_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 285 (grp), GIC_INTR_CFG_LEVEL) 286 287 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) 288 289 /* 290 * Required ARM CSS SoC based platform porting definitions 291 */ 292 293 /* CSS SoC NIC-400 Global Programmers View (GPV) */ 294 #define PLAT_SOC_CSS_NIC400_BASE UL(0x2a000000) 295 296 #define PLAT_ARM_PRIVATE_SDEI_EVENTS ARM_SDEI_PRIVATE_EVENTS 297 #define PLAT_ARM_SHARED_SDEI_EVENTS ARM_SDEI_SHARED_EVENTS 298 299 /* System power domain level */ 300 #define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2 301 302 #endif /* PLATFORM_DEF_H */ 303