1 /* 2 * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __PLATFORM_DEF_H__ 32 #define __PLATFORM_DEF_H__ 33 34 #include <arm_def.h> 35 #include <board_arm_def.h> 36 #include <board_css_def.h> 37 #include <common_def.h> 38 #include <css_def.h> 39 #include <soc_css_def.h> 40 #include <tzc400.h> 41 #include <v2m_def.h> 42 #include "../juno_def.h" 43 44 /* Juno supports system power domain */ 45 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL2 46 #define PLAT_NUM_PWR_DOMAINS (ARM_SYSTEM_COUNT + \ 47 ARM_CLUSTER_COUNT + \ 48 PLATFORM_CORE_COUNT) 49 /* 50 * Other platform porting definitions are provided by included headers 51 */ 52 53 /* 54 * Required ARM standard platform porting definitions 55 */ 56 #define PLAT_ARM_CLUSTER0_CORE_COUNT 2 57 #define PLAT_ARM_CLUSTER1_CORE_COUNT 4 58 59 /* Use the bypass address */ 60 #define PLAT_ARM_TRUSTED_ROM_BASE V2M_FLASH0_BASE + BL1_ROM_BYPASS_OFFSET 61 62 /* 63 * Actual ROM size on Juno is 64 KB, but TBB currently requires at least 80 KB 64 * in debug mode. We can test TBB on Juno bypassing the ROM and using 128 KB of 65 * flash 66 */ 67 #if TRUSTED_BOARD_BOOT 68 #define PLAT_ARM_TRUSTED_ROM_SIZE 0x00020000 69 #else 70 #define PLAT_ARM_TRUSTED_ROM_SIZE 0x00010000 71 #endif /* TRUSTED_BOARD_BOOT */ 72 73 /* 74 * If ARM_BOARD_OPTIMISE_MMAP=0 then Juno uses the default, unoptimised values 75 * defined for ARM development platforms. 76 */ 77 #if ARM_BOARD_OPTIMISE_MMAP 78 /* 79 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the 80 * plat_arm_mmap array defined for each BL stage. 81 */ 82 #if IMAGE_BL1 83 # define PLAT_ARM_MMAP_ENTRIES 7 84 # define MAX_XLAT_TABLES 4 85 #endif 86 87 #if IMAGE_BL2 88 # define PLAT_ARM_MMAP_ENTRIES 8 89 # define MAX_XLAT_TABLES 3 90 #endif 91 92 #if IMAGE_BL2U 93 # define PLAT_ARM_MMAP_ENTRIES 4 94 # define MAX_XLAT_TABLES 3 95 #endif 96 97 #if IMAGE_BL31 98 # define PLAT_ARM_MMAP_ENTRIES 5 99 # define MAX_XLAT_TABLES 2 100 #endif 101 102 #if IMAGE_BL32 103 # define PLAT_ARM_MMAP_ENTRIES 4 104 # define MAX_XLAT_TABLES 3 105 #endif 106 107 #endif /* ARM_BOARD_OPTIMISE_MMAP */ 108 109 /* CCI related constants */ 110 #define PLAT_ARM_CCI_BASE 0x2c090000 111 #define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 4 112 #define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 3 113 114 /* System timer related constants */ 115 #define PLAT_ARM_NSTIMER_FRAME_ID 1 116 117 /* TZC related constants */ 118 #define PLAT_ARM_TZC_BASE 0x2a4a0000 119 #define PLAT_ARM_TZC_NS_DEV_ACCESS ( \ 120 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CCI400) | \ 121 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_PCIE) | \ 122 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD0) | \ 123 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD1) | \ 124 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_USB) | \ 125 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_DMA330) | \ 126 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_THINLINKS) | \ 127 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_AP) | \ 128 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_GPU) | \ 129 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CORESIGHT)) 130 131 /* 132 * Required ARM CSS based platform porting definitions 133 */ 134 135 /* GIC related constants (no GICR in GIC-400) */ 136 #define PLAT_ARM_GICD_BASE 0x2c010000 137 #define PLAT_ARM_GICC_BASE 0x2c02f000 138 #define PLAT_ARM_GICH_BASE 0x2c04f000 139 #define PLAT_ARM_GICV_BASE 0x2c06f000 140 141 /* MHU related constants */ 142 #define PLAT_CSS_MHU_BASE 0x2b1f0000 143 144 /* 145 * Base address of the first memory region used for communication between AP 146 * and SCP. Used by the BOM and SCPI protocols. 147 * 148 * Note that this is located at the same address as SCP_BOOT_CFG_ADDR, which 149 * means the SCP/AP configuration data gets overwritten when the AP initiates 150 * communication with the SCP. The configuration data is expected to be a 151 * 32-bit word on all CSS platforms. On Juno, part of this configuration is 152 * which CPU is the primary, according to the shift and mask definitions below. 153 */ 154 #define PLAT_CSS_SCP_COM_SHARED_MEM_BASE (ARM_TRUSTED_SRAM_BASE + 0x80) 155 #define PLAT_CSS_PRIMARY_CPU_SHIFT 8 156 #define PLAT_CSS_PRIMARY_CPU_BIT_WIDTH 4 157 158 /* 159 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 160 * terminology. On a GICv2 system or mode, the lists will be merged and treated 161 * as Group 0 interrupts. 162 */ 163 #define PLAT_ARM_G1S_IRQS CSS_G1S_IRQS, \ 164 ARM_G1S_IRQS, \ 165 JUNO_IRQ_DMA_SMMU, \ 166 JUNO_IRQ_HDLCD0_SMMU, \ 167 JUNO_IRQ_HDLCD1_SMMU, \ 168 JUNO_IRQ_USB_SMMU, \ 169 JUNO_IRQ_THIN_LINKS_SMMU, \ 170 JUNO_IRQ_SEC_I2C, \ 171 JUNO_IRQ_GPU_SMMU_1, \ 172 JUNO_IRQ_ETR_SMMU 173 174 #define PLAT_ARM_G0_IRQS ARM_G0_IRQS 175 176 /* 177 * Required ARM CSS SoC based platform porting definitions 178 */ 179 180 /* CSS SoC NIC-400 Global Programmers View (GPV) */ 181 #define PLAT_SOC_CSS_NIC400_BASE 0x2a000000 182 183 /* 184 * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size 185 * plus a little space for growth. 186 */ 187 #if TRUSTED_BOARD_BOOT 188 # define PLAT_ARM_MAX_BL1_RW_SIZE 0x9000 189 #else 190 # define PLAT_ARM_MAX_BL1_RW_SIZE 0x6000 191 #endif 192 193 /* 194 * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a 195 * little space for growth. 196 */ 197 #if TRUSTED_BOARD_BOOT 198 # define PLAT_ARM_MAX_BL2_SIZE 0x1D000 199 #else 200 # define PLAT_ARM_MAX_BL2_SIZE 0xC000 201 #endif 202 203 /* 204 * PLAT_ARM_MAX_BL31_SIZE is calculated using the current BL31 debug size plus a 205 * little space for growth. 206 */ 207 #define PLAT_ARM_MAX_BL31_SIZE 0x1D000 208 209 #endif /* __PLATFORM_DEF_H__ */ 210