1 /* 2 * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 /* Enable the dynamic translation tables library. */ 11 #ifdef AARCH32 12 # if defined(IMAGE_BL32) && RESET_TO_SP_MIN 13 # define PLAT_XLAT_TABLES_DYNAMIC 1 14 # endif 15 #else 16 # if defined(IMAGE_BL31) && RESET_TO_BL31 17 # define PLAT_XLAT_TABLES_DYNAMIC 1 18 # endif 19 #endif /* AARCH32 */ 20 21 22 #include <arm_def.h> 23 #include <board_css_def.h> 24 #include <common_def.h> 25 #include <css_def.h> 26 #if TRUSTED_BOARD_BOOT 27 #include <mbedtls_config.h> 28 #endif 29 #include <soc_css_def.h> 30 #include <tzc400.h> 31 #include <v2m_def.h> 32 #include "../juno_def.h" 33 34 /* Required platform porting definitions */ 35 /* Juno supports system power domain */ 36 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL2 37 #define PLAT_NUM_PWR_DOMAINS (ARM_SYSTEM_COUNT + \ 38 JUNO_CLUSTER_COUNT + \ 39 PLATFORM_CORE_COUNT) 40 #define PLATFORM_CORE_COUNT (JUNO_CLUSTER0_CORE_COUNT + \ 41 JUNO_CLUSTER1_CORE_COUNT) 42 43 /* Cryptocell HW Base address */ 44 #define PLAT_CRYPTOCELL_BASE UL(0x60050000) 45 46 /* 47 * Other platform porting definitions are provided by included headers 48 */ 49 50 /* 51 * Required ARM standard platform porting definitions 52 */ 53 #define PLAT_ARM_CLUSTER_COUNT JUNO_CLUSTER_COUNT 54 55 #define PLAT_ARM_TRUSTED_SRAM_SIZE UL(0x00040000) /* 256 KB */ 56 57 /* Use the bypass address */ 58 #define PLAT_ARM_TRUSTED_ROM_BASE V2M_FLASH0_BASE + BL1_ROM_BYPASS_OFFSET 59 60 #define NSRAM_BASE UL(0x2e000000) 61 #define NSRAM_SIZE UL(0x00008000) /* 32KB */ 62 63 /* virtual address used by dynamic mem_protect for chunk_base */ 64 #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000) 65 66 /* 67 * Actual ROM size on Juno is 64 KB, but TBB currently requires at least 80 KB 68 * in debug mode. We can test TBB on Juno bypassing the ROM and using 128 KB of 69 * flash 70 */ 71 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE 0 72 73 #if TRUSTED_BOARD_BOOT 74 #define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x00020000) 75 #else 76 #define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x00010000) 77 #endif /* TRUSTED_BOARD_BOOT */ 78 79 /* 80 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the 81 * plat_arm_mmap array defined for each BL stage. 82 */ 83 #ifdef IMAGE_BL1 84 # define PLAT_ARM_MMAP_ENTRIES 7 85 # define MAX_XLAT_TABLES 4 86 #endif 87 88 #ifdef IMAGE_BL2 89 #ifdef SPD_opteed 90 # define PLAT_ARM_MMAP_ENTRIES 11 91 # define MAX_XLAT_TABLES 5 92 #else 93 # define PLAT_ARM_MMAP_ENTRIES 10 94 # define MAX_XLAT_TABLES 4 95 #endif 96 #endif 97 98 #ifdef IMAGE_BL2U 99 # define PLAT_ARM_MMAP_ENTRIES 5 100 # define MAX_XLAT_TABLES 3 101 #endif 102 103 #ifdef IMAGE_BL31 104 # define PLAT_ARM_MMAP_ENTRIES 7 105 # define MAX_XLAT_TABLES 3 106 #endif 107 108 #ifdef IMAGE_BL32 109 # define PLAT_ARM_MMAP_ENTRIES 6 110 # define MAX_XLAT_TABLES 4 111 #endif 112 113 /* 114 * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size 115 * plus a little space for growth. 116 */ 117 #if TRUSTED_BOARD_BOOT 118 # define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xB000) 119 #else 120 # define PLAT_ARM_MAX_BL1_RW_SIZE UL(0x6000) 121 #endif 122 123 /* 124 * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page 125 */ 126 #if USE_ROMLIB 127 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0x1000) 128 #else 129 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0) 130 #endif 131 132 /* 133 * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a 134 * little space for growth. 135 */ 136 #if TRUSTED_BOARD_BOOT 137 #if TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA 138 # define PLAT_ARM_MAX_BL2_SIZE UL(0x1F000) 139 #elif TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_ECDSA 140 # define PLAT_ARM_MAX_BL2_SIZE UL(0x1D000) 141 #else 142 # define PLAT_ARM_MAX_BL2_SIZE UL(0x1C000) 143 #endif 144 #else 145 # define PLAT_ARM_MAX_BL2_SIZE UL(0xF000) 146 #endif 147 148 /* 149 * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is 150 * calculated using the current BL31 PROGBITS debug size plus the sizes of 151 * BL2 and BL1-RW. SCP_BL2 image is loaded into the space BL31 -> BL2_BASE. 152 * Hence the BL31 PROGBITS size should be >= PLAT_CSS_MAX_SCP_BL2_SIZE. 153 */ 154 #define PLAT_ARM_MAX_BL31_SIZE UL(0x3E000) 155 156 #if JUNO_AARCH32_EL3_RUNTIME 157 /* 158 * Since BL32 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL32_SIZE is 159 * calculated using the current BL32 PROGBITS debug size plus the sizes of 160 * BL2 and BL1-RW. SCP_BL2 image is loaded into the space BL32 -> BL2_BASE. 161 * Hence the BL32 PROGBITS size should be >= PLAT_CSS_MAX_SCP_BL2_SIZE. 162 */ 163 #define PLAT_ARM_MAX_BL32_SIZE UL(0x3E000) 164 #endif 165 166 /* 167 * Size of cacheable stacks 168 */ 169 #if defined(IMAGE_BL1) 170 # if TRUSTED_BOARD_BOOT 171 # define PLATFORM_STACK_SIZE UL(0x1000) 172 # else 173 # define PLATFORM_STACK_SIZE UL(0x440) 174 # endif 175 #elif defined(IMAGE_BL2) 176 # if TRUSTED_BOARD_BOOT 177 # define PLATFORM_STACK_SIZE UL(0x1000) 178 # else 179 # define PLATFORM_STACK_SIZE UL(0x400) 180 # endif 181 #elif defined(IMAGE_BL2U) 182 # define PLATFORM_STACK_SIZE UL(0x400) 183 #elif defined(IMAGE_BL31) 184 # if PLAT_XLAT_TABLES_DYNAMIC 185 # define PLATFORM_STACK_SIZE UL(0x800) 186 # else 187 # define PLATFORM_STACK_SIZE UL(0x400) 188 # endif 189 #elif defined(IMAGE_BL32) 190 # define PLATFORM_STACK_SIZE UL(0x440) 191 #endif 192 193 /* 194 * Since free SRAM space is scant, enable the ASSERTION message size 195 * optimization by fixing the PLAT_LOG_LEVEL_ASSERT to LOG_LEVEL_INFO (40). 196 */ 197 #define PLAT_LOG_LEVEL_ASSERT 40 198 199 /* CCI related constants */ 200 #define PLAT_ARM_CCI_BASE UL(0x2c090000) 201 #define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 4 202 #define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 3 203 204 /* System timer related constants */ 205 #define PLAT_ARM_NSTIMER_FRAME_ID 1 206 207 /* TZC related constants */ 208 #define PLAT_ARM_TZC_BASE UL(0x2a4a0000) 209 #define PLAT_ARM_TZC_NS_DEV_ACCESS ( \ 210 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CCI400) | \ 211 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_PCIE) | \ 212 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD0) | \ 213 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD1) | \ 214 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_USB) | \ 215 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_DMA330) | \ 216 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_THINLINKS) | \ 217 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_AP) | \ 218 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_GPU) | \ 219 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CORESIGHT)) 220 221 /* 222 * Required ARM CSS based platform porting definitions 223 */ 224 225 /* GIC related constants (no GICR in GIC-400) */ 226 #define PLAT_ARM_GICD_BASE UL(0x2c010000) 227 #define PLAT_ARM_GICC_BASE UL(0x2c02f000) 228 #define PLAT_ARM_GICH_BASE UL(0x2c04f000) 229 #define PLAT_ARM_GICV_BASE UL(0x2c06f000) 230 231 /* MHU related constants */ 232 #define PLAT_CSS_MHU_BASE UL(0x2b1f0000) 233 234 /* 235 * Base address of the first memory region used for communication between AP 236 * and SCP. Used by the BOM and SCPI protocols. 237 */ 238 #if !CSS_USE_SCMI_SDS_DRIVER 239 /* 240 * Note that this is located at the same address as SCP_BOOT_CFG_ADDR, which 241 * means the SCP/AP configuration data gets overwritten when the AP initiates 242 * communication with the SCP. The configuration data is expected to be a 243 * 32-bit word on all CSS platforms. On Juno, part of this configuration is 244 * which CPU is the primary, according to the shift and mask definitions below. 245 */ 246 #define PLAT_CSS_SCP_COM_SHARED_MEM_BASE (ARM_TRUSTED_SRAM_BASE + UL(0x80)) 247 #define PLAT_CSS_PRIMARY_CPU_SHIFT 8 248 #define PLAT_CSS_PRIMARY_CPU_BIT_WIDTH 4 249 #endif 250 251 /* 252 * PLAT_CSS_MAX_SCP_BL2_SIZE is calculated using the current 253 * SCP_BL2 size plus a little space for growth. 254 */ 255 #define PLAT_CSS_MAX_SCP_BL2_SIZE UL(0x14000) 256 257 /* 258 * PLAT_CSS_MAX_SCP_BL2U_SIZE is calculated using the current 259 * SCP_BL2U size plus a little space for growth. 260 */ 261 #define PLAT_CSS_MAX_SCP_BL2U_SIZE UL(0x14000) 262 263 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 264 CSS_G1S_IRQ_PROPS(grp), \ 265 ARM_G1S_IRQ_PROPS(grp), \ 266 INTR_PROP_DESC(JUNO_IRQ_DMA_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 267 (grp), GIC_INTR_CFG_LEVEL), \ 268 INTR_PROP_DESC(JUNO_IRQ_HDLCD0_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 269 (grp), GIC_INTR_CFG_LEVEL), \ 270 INTR_PROP_DESC(JUNO_IRQ_HDLCD1_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 271 (grp), GIC_INTR_CFG_LEVEL), \ 272 INTR_PROP_DESC(JUNO_IRQ_USB_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 273 (grp), GIC_INTR_CFG_LEVEL), \ 274 INTR_PROP_DESC(JUNO_IRQ_THIN_LINKS_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 275 (grp), GIC_INTR_CFG_LEVEL), \ 276 INTR_PROP_DESC(JUNO_IRQ_SEC_I2C, GIC_HIGHEST_SEC_PRIORITY, \ 277 (grp), GIC_INTR_CFG_LEVEL), \ 278 INTR_PROP_DESC(JUNO_IRQ_GPU_SMMU_1, GIC_HIGHEST_SEC_PRIORITY, \ 279 (grp), GIC_INTR_CFG_LEVEL), \ 280 INTR_PROP_DESC(JUNO_IRQ_ETR_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 281 (grp), GIC_INTR_CFG_LEVEL) 282 283 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) 284 285 /* 286 * Required ARM CSS SoC based platform porting definitions 287 */ 288 289 /* CSS SoC NIC-400 Global Programmers View (GPV) */ 290 #define PLAT_SOC_CSS_NIC400_BASE UL(0x2a000000) 291 292 #define PLAT_ARM_PRIVATE_SDEI_EVENTS ARM_SDEI_PRIVATE_EVENTS 293 #define PLAT_ARM_SHARED_SDEI_EVENTS ARM_SDEI_SHARED_EVENTS 294 295 #endif /* PLATFORM_DEF_H */ 296