1 /* 2 * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __PLATFORM_DEF_H__ 32 #define __PLATFORM_DEF_H__ 33 34 #include <arm_def.h> 35 #include <board_arm_def.h> 36 #include <board_css_def.h> 37 #include <common_def.h> 38 #include <css_def.h> 39 #include <soc_css_def.h> 40 #include <tzc400.h> 41 #include <v2m_def.h> 42 #include "../juno_def.h" 43 44 /* Required platform porting definitions */ 45 /* Juno supports system power domain */ 46 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL2 47 #define PLAT_NUM_PWR_DOMAINS (ARM_SYSTEM_COUNT + \ 48 JUNO_CLUSTER_COUNT + \ 49 PLATFORM_CORE_COUNT) 50 #define PLATFORM_CORE_COUNT (JUNO_CLUSTER0_CORE_COUNT + \ 51 JUNO_CLUSTER1_CORE_COUNT) 52 53 /* 54 * Other platform porting definitions are provided by included headers 55 */ 56 57 /* 58 * Required ARM standard platform porting definitions 59 */ 60 #define PLAT_ARM_CLUSTER_COUNT JUNO_CLUSTER_COUNT 61 62 /* Use the bypass address */ 63 #define PLAT_ARM_TRUSTED_ROM_BASE V2M_FLASH0_BASE + BL1_ROM_BYPASS_OFFSET 64 65 /* 66 * Actual ROM size on Juno is 64 KB, but TBB currently requires at least 80 KB 67 * in debug mode. We can test TBB on Juno bypassing the ROM and using 128 KB of 68 * flash 69 */ 70 #if TRUSTED_BOARD_BOOT 71 #define PLAT_ARM_TRUSTED_ROM_SIZE 0x00020000 72 #else 73 #define PLAT_ARM_TRUSTED_ROM_SIZE 0x00010000 74 #endif /* TRUSTED_BOARD_BOOT */ 75 76 /* 77 * If ARM_BOARD_OPTIMISE_MMAP=0 then Juno uses the default, unoptimised values 78 * defined for ARM development platforms. 79 */ 80 #if ARM_BOARD_OPTIMISE_MMAP 81 /* 82 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the 83 * plat_arm_mmap array defined for each BL stage. 84 */ 85 #if IMAGE_BL1 86 # define PLAT_ARM_MMAP_ENTRIES 7 87 # define MAX_XLAT_TABLES 4 88 #endif 89 90 #if IMAGE_BL2 91 # define PLAT_ARM_MMAP_ENTRIES 8 92 # define MAX_XLAT_TABLES 3 93 #endif 94 95 #if IMAGE_BL2U 96 # define PLAT_ARM_MMAP_ENTRIES 4 97 # define MAX_XLAT_TABLES 3 98 #endif 99 100 #if IMAGE_BL31 101 # define PLAT_ARM_MMAP_ENTRIES 5 102 # define MAX_XLAT_TABLES 2 103 #endif 104 105 #if IMAGE_BL32 106 # define PLAT_ARM_MMAP_ENTRIES 4 107 # define MAX_XLAT_TABLES 3 108 #endif 109 110 #endif /* ARM_BOARD_OPTIMISE_MMAP */ 111 112 /* CCI related constants */ 113 #define PLAT_ARM_CCI_BASE 0x2c090000 114 #define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 4 115 #define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 3 116 117 /* System timer related constants */ 118 #define PLAT_ARM_NSTIMER_FRAME_ID 1 119 120 /* TZC related constants */ 121 #define PLAT_ARM_TZC_BASE 0x2a4a0000 122 #define PLAT_ARM_TZC_NS_DEV_ACCESS ( \ 123 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CCI400) | \ 124 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_PCIE) | \ 125 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD0) | \ 126 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD1) | \ 127 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_USB) | \ 128 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_DMA330) | \ 129 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_THINLINKS) | \ 130 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_AP) | \ 131 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_GPU) | \ 132 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CORESIGHT)) 133 134 /* 135 * Required ARM CSS based platform porting definitions 136 */ 137 138 /* GIC related constants (no GICR in GIC-400) */ 139 #define PLAT_ARM_GICD_BASE 0x2c010000 140 #define PLAT_ARM_GICC_BASE 0x2c02f000 141 #define PLAT_ARM_GICH_BASE 0x2c04f000 142 #define PLAT_ARM_GICV_BASE 0x2c06f000 143 144 /* MHU related constants */ 145 #define PLAT_CSS_MHU_BASE 0x2b1f0000 146 147 /* 148 * Base address of the first memory region used for communication between AP 149 * and SCP. Used by the BOM and SCPI protocols. 150 * 151 * Note that this is located at the same address as SCP_BOOT_CFG_ADDR, which 152 * means the SCP/AP configuration data gets overwritten when the AP initiates 153 * communication with the SCP. The configuration data is expected to be a 154 * 32-bit word on all CSS platforms. On Juno, part of this configuration is 155 * which CPU is the primary, according to the shift and mask definitions below. 156 */ 157 #define PLAT_CSS_SCP_COM_SHARED_MEM_BASE (ARM_TRUSTED_SRAM_BASE + 0x80) 158 #define PLAT_CSS_PRIMARY_CPU_SHIFT 8 159 #define PLAT_CSS_PRIMARY_CPU_BIT_WIDTH 4 160 161 /* 162 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 163 * terminology. On a GICv2 system or mode, the lists will be merged and treated 164 * as Group 0 interrupts. 165 */ 166 #define PLAT_ARM_G1S_IRQS CSS_G1S_IRQS, \ 167 ARM_G1S_IRQS, \ 168 JUNO_IRQ_DMA_SMMU, \ 169 JUNO_IRQ_HDLCD0_SMMU, \ 170 JUNO_IRQ_HDLCD1_SMMU, \ 171 JUNO_IRQ_USB_SMMU, \ 172 JUNO_IRQ_THIN_LINKS_SMMU, \ 173 JUNO_IRQ_SEC_I2C, \ 174 JUNO_IRQ_GPU_SMMU_1, \ 175 JUNO_IRQ_ETR_SMMU 176 177 #define PLAT_ARM_G0_IRQS ARM_G0_IRQS 178 179 /* 180 * Required ARM CSS SoC based platform porting definitions 181 */ 182 183 /* CSS SoC NIC-400 Global Programmers View (GPV) */ 184 #define PLAT_SOC_CSS_NIC400_BASE 0x2a000000 185 186 /* 187 * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size 188 * plus a little space for growth. 189 */ 190 #if TRUSTED_BOARD_BOOT 191 # define PLAT_ARM_MAX_BL1_RW_SIZE 0x9000 192 #else 193 # define PLAT_ARM_MAX_BL1_RW_SIZE 0x6000 194 #endif 195 196 /* 197 * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a 198 * little space for growth. 199 */ 200 #if TRUSTED_BOARD_BOOT 201 # define PLAT_ARM_MAX_BL2_SIZE 0x1D000 202 #else 203 # define PLAT_ARM_MAX_BL2_SIZE 0xC000 204 #endif 205 206 /* 207 * PLAT_ARM_MAX_BL31_SIZE is calculated using the current BL31 debug size plus a 208 * little space for growth. 209 */ 210 #define PLAT_ARM_MAX_BL31_SIZE 0x1D000 211 212 #endif /* __PLATFORM_DEF_H__ */ 213