1 /* 2 * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __PLATFORM_DEF_H__ 8 #define __PLATFORM_DEF_H__ 9 10 /* Enable the dynamic translation tables library. */ 11 #ifdef AARCH32 12 # if defined(IMAGE_BL32) && RESET_TO_SP_MIN 13 # define PLAT_XLAT_TABLES_DYNAMIC 1 14 # endif 15 #else 16 # if defined(IMAGE_BL31) && RESET_TO_BL31 17 # define PLAT_XLAT_TABLES_DYNAMIC 1 18 # endif 19 #endif /* AARCH32 */ 20 21 22 #include <arm_def.h> 23 #include <board_arm_def.h> 24 #include <board_css_def.h> 25 #include <common_def.h> 26 #include <css_def.h> 27 #if TRUSTED_BOARD_BOOT 28 #include <mbedtls_config.h> 29 #endif 30 #include <soc_css_def.h> 31 #include <tzc400.h> 32 #include <v2m_def.h> 33 #include "../juno_def.h" 34 35 /* Required platform porting definitions */ 36 /* Juno supports system power domain */ 37 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL2 38 #define PLAT_NUM_PWR_DOMAINS (ARM_SYSTEM_COUNT + \ 39 JUNO_CLUSTER_COUNT + \ 40 PLATFORM_CORE_COUNT) 41 #define PLATFORM_CORE_COUNT (JUNO_CLUSTER0_CORE_COUNT + \ 42 JUNO_CLUSTER1_CORE_COUNT) 43 44 /* Cryptocell HW Base address */ 45 #define PLAT_CRYPTOCELL_BASE 0x60050000 46 47 /* 48 * Other platform porting definitions are provided by included headers 49 */ 50 51 /* 52 * Required ARM standard platform porting definitions 53 */ 54 #define PLAT_ARM_CLUSTER_COUNT JUNO_CLUSTER_COUNT 55 56 /* Use the bypass address */ 57 #define PLAT_ARM_TRUSTED_ROM_BASE V2M_FLASH0_BASE + BL1_ROM_BYPASS_OFFSET 58 59 #define NSRAM_BASE 0x2e000000 60 #define NSRAM_SIZE 0x00008000 /* 32KB */ 61 62 /* virtual address used by dynamic mem_protect for chunk_base */ 63 #define PLAT_ARM_MEM_PROTEC_VA_FRAME 0xc0000000 64 65 /* 66 * Actual ROM size on Juno is 64 KB, but TBB currently requires at least 80 KB 67 * in debug mode. We can test TBB on Juno bypassing the ROM and using 128 KB of 68 * flash 69 */ 70 #if TRUSTED_BOARD_BOOT 71 #define PLAT_ARM_TRUSTED_ROM_SIZE 0x00020000 72 #else 73 #define PLAT_ARM_TRUSTED_ROM_SIZE 0x00010000 74 #endif /* TRUSTED_BOARD_BOOT */ 75 76 /* 77 * If ARM_BOARD_OPTIMISE_MEM=0 then Juno uses the default, unoptimised values 78 * defined for ARM development platforms. 79 */ 80 #if ARM_BOARD_OPTIMISE_MEM 81 /* 82 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the 83 * plat_arm_mmap array defined for each BL stage. 84 */ 85 #ifdef IMAGE_BL1 86 # define PLAT_ARM_MMAP_ENTRIES 7 87 # define MAX_XLAT_TABLES 4 88 #endif 89 90 #ifdef IMAGE_BL2 91 #ifdef SPD_opteed 92 # define PLAT_ARM_MMAP_ENTRIES 11 93 # define MAX_XLAT_TABLES 5 94 #else 95 # define PLAT_ARM_MMAP_ENTRIES 10 96 # define MAX_XLAT_TABLES 4 97 #endif 98 #endif 99 100 #ifdef IMAGE_BL2U 101 # define PLAT_ARM_MMAP_ENTRIES 5 102 # define MAX_XLAT_TABLES 3 103 #endif 104 105 #ifdef IMAGE_BL31 106 # define PLAT_ARM_MMAP_ENTRIES 7 107 # define MAX_XLAT_TABLES 3 108 #endif 109 110 #ifdef IMAGE_BL32 111 # define PLAT_ARM_MMAP_ENTRIES 6 112 # define MAX_XLAT_TABLES 4 113 #endif 114 115 /* 116 * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size 117 * plus a little space for growth. 118 */ 119 #if TRUSTED_BOARD_BOOT 120 # define PLAT_ARM_MAX_BL1_RW_SIZE 0xB000 121 #else 122 # define PLAT_ARM_MAX_BL1_RW_SIZE 0x6000 123 #endif 124 125 /* 126 * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a 127 * little space for growth. 128 */ 129 #if TRUSTED_BOARD_BOOT 130 #if TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA 131 # define PLAT_ARM_MAX_BL2_SIZE 0x1F000 132 #elif TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_ECDSA 133 # define PLAT_ARM_MAX_BL2_SIZE 0x1D000 134 #else 135 # define PLAT_ARM_MAX_BL2_SIZE 0x1C000 136 #endif 137 #else 138 # define PLAT_ARM_MAX_BL2_SIZE 0xE000 139 #endif 140 141 /* 142 * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is 143 * calculated using the current BL31 PROGBITS debug size plus the sizes of 144 * BL2 and BL1-RW. SCP_BL2 image is loaded into the space BL31 -> BL2_BASE. 145 * Hence the BL31 PROGBITS size should be >= PLAT_CSS_MAX_SCP_BL2_SIZE. 146 */ 147 #define PLAT_ARM_MAX_BL31_SIZE 0x3E000 148 149 #if JUNO_AARCH32_EL3_RUNTIME 150 /* 151 * Since BL32 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL32_SIZE is 152 * calculated using the current BL32 PROGBITS debug size plus the sizes of 153 * BL2 and BL1-RW. SCP_BL2 image is loaded into the space BL32 -> BL2_BASE. 154 * Hence the BL32 PROGBITS size should be >= PLAT_CSS_MAX_SCP_BL2_SIZE. 155 */ 156 #define PLAT_ARM_MAX_BL32_SIZE 0x3E000 157 #endif 158 159 /* 160 * Since free SRAM space is scant, enable the ASSERTION message size 161 * optimization by fixing the PLAT_LOG_LEVEL_ASSERT to LOG_LEVEL_INFO (40). 162 */ 163 #define PLAT_LOG_LEVEL_ASSERT 40 164 165 #endif /* ARM_BOARD_OPTIMISE_MEM */ 166 167 /* CCI related constants */ 168 #define PLAT_ARM_CCI_BASE 0x2c090000 169 #define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 4 170 #define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 3 171 172 /* System timer related constants */ 173 #define PLAT_ARM_NSTIMER_FRAME_ID 1 174 175 /* TZC related constants */ 176 #define PLAT_ARM_TZC_BASE 0x2a4a0000 177 #define PLAT_ARM_TZC_NS_DEV_ACCESS ( \ 178 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CCI400) | \ 179 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_PCIE) | \ 180 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD0) | \ 181 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD1) | \ 182 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_USB) | \ 183 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_DMA330) | \ 184 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_THINLINKS) | \ 185 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_AP) | \ 186 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_GPU) | \ 187 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CORESIGHT)) 188 189 /* 190 * Required ARM CSS based platform porting definitions 191 */ 192 193 /* GIC related constants (no GICR in GIC-400) */ 194 #define PLAT_ARM_GICD_BASE 0x2c010000 195 #define PLAT_ARM_GICC_BASE 0x2c02f000 196 #define PLAT_ARM_GICH_BASE 0x2c04f000 197 #define PLAT_ARM_GICV_BASE 0x2c06f000 198 199 /* MHU related constants */ 200 #define PLAT_CSS_MHU_BASE 0x2b1f0000 201 202 /* 203 * Base address of the first memory region used for communication between AP 204 * and SCP. Used by the BOM and SCPI protocols. 205 */ 206 #if !CSS_USE_SCMI_SDS_DRIVER 207 /* 208 * Note that this is located at the same address as SCP_BOOT_CFG_ADDR, which 209 * means the SCP/AP configuration data gets overwritten when the AP initiates 210 * communication with the SCP. The configuration data is expected to be a 211 * 32-bit word on all CSS platforms. On Juno, part of this configuration is 212 * which CPU is the primary, according to the shift and mask definitions below. 213 */ 214 #define PLAT_CSS_SCP_COM_SHARED_MEM_BASE (ARM_TRUSTED_SRAM_BASE + 0x80) 215 #define PLAT_CSS_PRIMARY_CPU_SHIFT 8 216 #define PLAT_CSS_PRIMARY_CPU_BIT_WIDTH 4 217 #endif 218 219 /* 220 * PLAT_CSS_MAX_SCP_BL2_SIZE is calculated using the current 221 * SCP_BL2 size plus a little space for growth. 222 */ 223 #define PLAT_CSS_MAX_SCP_BL2_SIZE 0x14000 224 225 /* 226 * PLAT_CSS_MAX_SCP_BL2U_SIZE is calculated using the current 227 * SCP_BL2U size plus a little space for growth. 228 */ 229 #define PLAT_CSS_MAX_SCP_BL2U_SIZE 0x14000 230 231 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 232 CSS_G1S_IRQ_PROPS(grp), \ 233 ARM_G1S_IRQ_PROPS(grp), \ 234 INTR_PROP_DESC(JUNO_IRQ_DMA_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 235 grp, GIC_INTR_CFG_LEVEL), \ 236 INTR_PROP_DESC(JUNO_IRQ_HDLCD0_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 237 grp, GIC_INTR_CFG_LEVEL), \ 238 INTR_PROP_DESC(JUNO_IRQ_HDLCD1_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 239 grp, GIC_INTR_CFG_LEVEL), \ 240 INTR_PROP_DESC(JUNO_IRQ_USB_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 241 grp, GIC_INTR_CFG_LEVEL), \ 242 INTR_PROP_DESC(JUNO_IRQ_THIN_LINKS_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 243 grp, GIC_INTR_CFG_LEVEL), \ 244 INTR_PROP_DESC(JUNO_IRQ_SEC_I2C, GIC_HIGHEST_SEC_PRIORITY, \ 245 grp, GIC_INTR_CFG_LEVEL), \ 246 INTR_PROP_DESC(JUNO_IRQ_GPU_SMMU_1, GIC_HIGHEST_SEC_PRIORITY, \ 247 grp, GIC_INTR_CFG_LEVEL), \ 248 INTR_PROP_DESC(JUNO_IRQ_ETR_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 249 grp, GIC_INTR_CFG_LEVEL) 250 251 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) 252 253 /* 254 * Required ARM CSS SoC based platform porting definitions 255 */ 256 257 /* CSS SoC NIC-400 Global Programmers View (GPV) */ 258 #define PLAT_SOC_CSS_NIC400_BASE 0x2a000000 259 260 #define PLAT_ARM_PRIVATE_SDEI_EVENTS ARM_SDEI_PRIVATE_EVENTS 261 #define PLAT_ARM_SHARED_SDEI_EVENTS ARM_SDEI_SHARED_EVENTS 262 263 #endif /* __PLATFORM_DEF_H__ */ 264