1 /* 2 * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __PLATFORM_DEF_H__ 8 #define __PLATFORM_DEF_H__ 9 10 #include <arm_def.h> 11 #include <board_arm_def.h> 12 #include <board_css_def.h> 13 #include <common_def.h> 14 #include <css_def.h> 15 #include <soc_css_def.h> 16 #include <tzc400.h> 17 #include <v2m_def.h> 18 #include "../juno_def.h" 19 20 /* Required platform porting definitions */ 21 /* Juno supports system power domain */ 22 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL2 23 #define PLAT_NUM_PWR_DOMAINS (ARM_SYSTEM_COUNT + \ 24 JUNO_CLUSTER_COUNT + \ 25 PLATFORM_CORE_COUNT) 26 #define PLATFORM_CORE_COUNT (JUNO_CLUSTER0_CORE_COUNT + \ 27 JUNO_CLUSTER1_CORE_COUNT) 28 29 /* Cryptocell HW Base address */ 30 #define PLAT_CRYPTOCELL_BASE 0x60050000 31 32 /* 33 * Other platform porting definitions are provided by included headers 34 */ 35 36 /* 37 * Required ARM standard platform porting definitions 38 */ 39 #define PLAT_ARM_CLUSTER_COUNT JUNO_CLUSTER_COUNT 40 41 /* Use the bypass address */ 42 #define PLAT_ARM_TRUSTED_ROM_BASE V2M_FLASH0_BASE + BL1_ROM_BYPASS_OFFSET 43 44 /* 45 * Actual ROM size on Juno is 64 KB, but TBB currently requires at least 80 KB 46 * in debug mode. We can test TBB on Juno bypassing the ROM and using 128 KB of 47 * flash 48 */ 49 #if TRUSTED_BOARD_BOOT 50 #define PLAT_ARM_TRUSTED_ROM_SIZE 0x00020000 51 #else 52 #define PLAT_ARM_TRUSTED_ROM_SIZE 0x00010000 53 #endif /* TRUSTED_BOARD_BOOT */ 54 55 /* 56 * If ARM_BOARD_OPTIMISE_MEM=0 then Juno uses the default, unoptimised values 57 * defined for ARM development platforms. 58 */ 59 #if ARM_BOARD_OPTIMISE_MEM 60 /* 61 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the 62 * plat_arm_mmap array defined for each BL stage. 63 */ 64 #ifdef IMAGE_BL1 65 # define PLAT_ARM_MMAP_ENTRIES 7 66 # define MAX_XLAT_TABLES 4 67 #endif 68 69 #ifdef IMAGE_BL2 70 #ifdef SPD_opteed 71 # define PLAT_ARM_MMAP_ENTRIES 11 72 # define MAX_XLAT_TABLES 5 73 #else 74 # define PLAT_ARM_MMAP_ENTRIES 10 75 # define MAX_XLAT_TABLES 4 76 #endif 77 #endif 78 79 #ifdef IMAGE_BL2U 80 # define PLAT_ARM_MMAP_ENTRIES 4 81 # define MAX_XLAT_TABLES 3 82 #endif 83 84 #ifdef IMAGE_BL31 85 # define PLAT_ARM_MMAP_ENTRIES 7 86 # define MAX_XLAT_TABLES 3 87 #endif 88 89 #ifdef IMAGE_BL32 90 # define PLAT_ARM_MMAP_ENTRIES 5 91 # define MAX_XLAT_TABLES 4 92 #endif 93 94 /* 95 * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size 96 * plus a little space for growth. 97 */ 98 #if TRUSTED_BOARD_BOOT 99 # define PLAT_ARM_MAX_BL1_RW_SIZE 0xA000 100 #else 101 # define PLAT_ARM_MAX_BL1_RW_SIZE 0x6000 102 #endif 103 104 /* 105 * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a 106 * little space for growth. 107 */ 108 #if TRUSTED_BOARD_BOOT 109 # define PLAT_ARM_MAX_BL2_SIZE 0x19000 110 #else 111 # define PLAT_ARM_MAX_BL2_SIZE 0xC000 112 #endif 113 114 /* 115 * PLAT_ARM_MAX_BL31_SIZE is calculated using the current BL31 debug size plus a 116 * little space for growth. 117 * SCP_BL2 image is loaded into the space BL31 -> BL1_RW_BASE. 118 * For TBB use case, PLAT_ARM_MAX_BL1_RW_SIZE has been increased and therefore 119 * PLAT_ARM_MAX_BL31_SIZE has been increased to ensure SCP_BL2 has the same 120 * space available. 121 */ 122 #define PLAT_ARM_MAX_BL31_SIZE 0x1E000 123 124 /* 125 * Since free SRAM space is scant, enable the ASSERTION message size 126 * optimization by fixing the PLAT_LOG_LEVEL_ASSERT to LOG_LEVEL_INFO (40). 127 */ 128 #define PLAT_LOG_LEVEL_ASSERT 40 129 130 #endif /* ARM_BOARD_OPTIMISE_MEM */ 131 132 /* CCI related constants */ 133 #define PLAT_ARM_CCI_BASE 0x2c090000 134 #define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 4 135 #define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 3 136 137 /* System timer related constants */ 138 #define PLAT_ARM_NSTIMER_FRAME_ID 1 139 140 /* TZC related constants */ 141 #define PLAT_ARM_TZC_BASE 0x2a4a0000 142 #define PLAT_ARM_TZC_NS_DEV_ACCESS ( \ 143 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CCI400) | \ 144 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_PCIE) | \ 145 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD0) | \ 146 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD1) | \ 147 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_USB) | \ 148 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_DMA330) | \ 149 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_THINLINKS) | \ 150 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_AP) | \ 151 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_GPU) | \ 152 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CORESIGHT)) 153 154 /* 155 * Required ARM CSS based platform porting definitions 156 */ 157 158 /* GIC related constants (no GICR in GIC-400) */ 159 #define PLAT_ARM_GICD_BASE 0x2c010000 160 #define PLAT_ARM_GICC_BASE 0x2c02f000 161 #define PLAT_ARM_GICH_BASE 0x2c04f000 162 #define PLAT_ARM_GICV_BASE 0x2c06f000 163 164 /* MHU related constants */ 165 #define PLAT_CSS_MHU_BASE 0x2b1f0000 166 167 /* 168 * Base address of the first memory region used for communication between AP 169 * and SCP. Used by the BOM and SCPI protocols. 170 */ 171 #if !CSS_USE_SCMI_SDS_DRIVER 172 /* 173 * Note that this is located at the same address as SCP_BOOT_CFG_ADDR, which 174 * means the SCP/AP configuration data gets overwritten when the AP initiates 175 * communication with the SCP. The configuration data is expected to be a 176 * 32-bit word on all CSS platforms. On Juno, part of this configuration is 177 * which CPU is the primary, according to the shift and mask definitions below. 178 */ 179 #define PLAT_CSS_SCP_COM_SHARED_MEM_BASE (ARM_TRUSTED_SRAM_BASE + 0x80) 180 #define PLAT_CSS_PRIMARY_CPU_SHIFT 8 181 #define PLAT_CSS_PRIMARY_CPU_BIT_WIDTH 4 182 #endif 183 184 /* 185 * PLAT_CSS_MAX_SCP_BL2_SIZE is calculated using the current 186 * SCP_BL2 size plus a little space for growth. 187 */ 188 #define PLAT_CSS_MAX_SCP_BL2_SIZE 0x14000 189 190 /* 191 * PLAT_CSS_MAX_SCP_BL2U_SIZE is calculated using the current 192 * SCP_BL2U size plus a little space for growth. 193 */ 194 #define PLAT_CSS_MAX_SCP_BL2U_SIZE 0x14000 195 196 /* 197 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 198 * terminology. On a GICv2 system or mode, the lists will be merged and treated 199 * as Group 0 interrupts. 200 */ 201 #define PLAT_ARM_G1S_IRQS CSS_G1S_IRQS, \ 202 ARM_G1S_IRQS, \ 203 JUNO_IRQ_DMA_SMMU, \ 204 JUNO_IRQ_HDLCD0_SMMU, \ 205 JUNO_IRQ_HDLCD1_SMMU, \ 206 JUNO_IRQ_USB_SMMU, \ 207 JUNO_IRQ_THIN_LINKS_SMMU, \ 208 JUNO_IRQ_SEC_I2C, \ 209 JUNO_IRQ_GPU_SMMU_1, \ 210 JUNO_IRQ_ETR_SMMU 211 212 #define PLAT_ARM_G0_IRQS ARM_G0_IRQS 213 214 /* 215 * Required ARM CSS SoC based platform porting definitions 216 */ 217 218 /* CSS SoC NIC-400 Global Programmers View (GPV) */ 219 #define PLAT_SOC_CSS_NIC400_BASE 0x2a000000 220 221 #endif /* __PLATFORM_DEF_H__ */ 222