1 /* 2 * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <drivers/arm/tzc400.h> 11 #if TRUSTED_BOARD_BOOT 12 #include <drivers/auth/mbedtls/mbedtls_config.h> 13 #endif 14 #include <plat/arm/board/common/board_css_def.h> 15 #include <plat/arm/board/common/v2m_def.h> 16 #include <plat/arm/common/arm_def.h> 17 #include <plat/arm/css/common/css_def.h> 18 #include <plat/arm/soc/common/soc_css_def.h> 19 #include <plat/common/common_def.h> 20 21 #include "../juno_def.h" 22 23 /* Required platform porting definitions */ 24 /* Juno supports system power domain */ 25 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL2 26 #define PLAT_NUM_PWR_DOMAINS (ARM_SYSTEM_COUNT + \ 27 JUNO_CLUSTER_COUNT + \ 28 PLATFORM_CORE_COUNT) 29 #define PLATFORM_CORE_COUNT (JUNO_CLUSTER0_CORE_COUNT + \ 30 JUNO_CLUSTER1_CORE_COUNT) 31 32 /* Cryptocell HW Base address */ 33 #define PLAT_CRYPTOCELL_BASE UL(0x60050000) 34 35 /* 36 * Other platform porting definitions are provided by included headers 37 */ 38 39 /* 40 * Required ARM standard platform porting definitions 41 */ 42 #define PLAT_ARM_CLUSTER_COUNT JUNO_CLUSTER_COUNT 43 44 #define PLAT_ARM_TRUSTED_SRAM_SIZE UL(0x00040000) /* 256 KB */ 45 46 /* Use the bypass address */ 47 #define PLAT_ARM_TRUSTED_ROM_BASE (V2M_FLASH0_BASE + \ 48 BL1_ROM_BYPASS_OFFSET) 49 50 #define NSRAM_BASE UL(0x2e000000) 51 #define NSRAM_SIZE UL(0x00008000) /* 32KB */ 52 53 /* virtual address used by dynamic mem_protect for chunk_base */ 54 #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000) 55 56 /* 57 * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page 58 */ 59 60 #if USE_ROMLIB 61 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0x1000) 62 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0xe000) 63 #define JUNO_BL2_ROMLIB_OPTIMIZATION UL(0x8000) 64 #else 65 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0) 66 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0) 67 #define JUNO_BL2_ROMLIB_OPTIMIZATION UL(0) 68 #endif 69 70 /* 71 * Actual ROM size on Juno is 64 KB, but TBB currently requires at least 80 KB 72 * in debug mode. We can test TBB on Juno bypassing the ROM and using 128 KB of 73 * flash 74 */ 75 76 #if TRUSTED_BOARD_BOOT 77 #define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x00020000) 78 #else 79 #define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x00010000) 80 #endif /* TRUSTED_BOARD_BOOT */ 81 82 /* 83 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the 84 * plat_arm_mmap array defined for each BL stage. 85 */ 86 #ifdef IMAGE_BL1 87 # define PLAT_ARM_MMAP_ENTRIES 7 88 # define MAX_XLAT_TABLES 4 89 #endif 90 91 #ifdef IMAGE_BL2 92 #ifdef SPD_opteed 93 # define PLAT_ARM_MMAP_ENTRIES 11 94 # define MAX_XLAT_TABLES 5 95 #else 96 # define PLAT_ARM_MMAP_ENTRIES 10 97 # define MAX_XLAT_TABLES 4 98 #endif 99 #endif 100 101 #ifdef IMAGE_BL2U 102 # define PLAT_ARM_MMAP_ENTRIES 5 103 # define MAX_XLAT_TABLES 3 104 #endif 105 106 #ifdef IMAGE_BL31 107 # define PLAT_ARM_MMAP_ENTRIES 7 108 # define MAX_XLAT_TABLES 3 109 #endif 110 111 #ifdef IMAGE_BL32 112 # define PLAT_ARM_MMAP_ENTRIES 6 113 # define MAX_XLAT_TABLES 4 114 #endif 115 116 /* 117 * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size 118 * plus a little space for growth. 119 */ 120 #if TRUSTED_BOARD_BOOT 121 # define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xB000) 122 #else 123 # define PLAT_ARM_MAX_BL1_RW_SIZE UL(0x6000) 124 #endif 125 126 /* 127 * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a 128 * little space for growth. 129 */ 130 #if TRUSTED_BOARD_BOOT 131 #if TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA 132 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1F000) - JUNO_BL2_ROMLIB_OPTIMIZATION) 133 #elif TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_ECDSA 134 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1D000) - JUNO_BL2_ROMLIB_OPTIMIZATION) 135 #else 136 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1D000) - JUNO_BL2_ROMLIB_OPTIMIZATION) 137 #endif 138 #else 139 # define PLAT_ARM_MAX_BL2_SIZE (UL(0xF000) - JUNO_BL2_ROMLIB_OPTIMIZATION) 140 #endif 141 142 /* 143 * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is 144 * calculated using the current BL31 PROGBITS debug size plus the sizes of 145 * BL2 and BL1-RW. SCP_BL2 image is loaded into the space BL31 -> BL2_BASE. 146 * Hence the BL31 PROGBITS size should be >= PLAT_CSS_MAX_SCP_BL2_SIZE. 147 */ 148 #define PLAT_ARM_MAX_BL31_SIZE UL(0x3E000) 149 150 #if JUNO_AARCH32_EL3_RUNTIME 151 /* 152 * Since BL32 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL32_SIZE is 153 * calculated using the current BL32 PROGBITS debug size plus the sizes of 154 * BL2 and BL1-RW. SCP_BL2 image is loaded into the space BL32 -> BL2_BASE. 155 * Hence the BL32 PROGBITS size should be >= PLAT_CSS_MAX_SCP_BL2_SIZE. 156 */ 157 #define PLAT_ARM_MAX_BL32_SIZE UL(0x3E000) 158 #endif 159 160 /* 161 * Size of cacheable stacks 162 */ 163 #if defined(IMAGE_BL1) 164 # if TRUSTED_BOARD_BOOT 165 # define PLATFORM_STACK_SIZE UL(0x1000) 166 # else 167 # define PLATFORM_STACK_SIZE UL(0x440) 168 # endif 169 #elif defined(IMAGE_BL2) 170 # if TRUSTED_BOARD_BOOT 171 # define PLATFORM_STACK_SIZE UL(0x1000) 172 # else 173 # define PLATFORM_STACK_SIZE UL(0x400) 174 # endif 175 #elif defined(IMAGE_BL2U) 176 # define PLATFORM_STACK_SIZE UL(0x400) 177 #elif defined(IMAGE_BL31) 178 # if PLAT_XLAT_TABLES_DYNAMIC 179 # define PLATFORM_STACK_SIZE UL(0x800) 180 # else 181 # define PLATFORM_STACK_SIZE UL(0x400) 182 # endif 183 #elif defined(IMAGE_BL32) 184 # define PLATFORM_STACK_SIZE UL(0x440) 185 #endif 186 187 /* 188 * Since free SRAM space is scant, enable the ASSERTION message size 189 * optimization by fixing the PLAT_LOG_LEVEL_ASSERT to LOG_LEVEL_INFO (40). 190 */ 191 #define PLAT_LOG_LEVEL_ASSERT 40 192 193 /* CCI related constants */ 194 #define PLAT_ARM_CCI_BASE UL(0x2c090000) 195 #define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 4 196 #define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 3 197 198 /* System timer related constants */ 199 #define PLAT_ARM_NSTIMER_FRAME_ID U(1) 200 201 /* TZC related constants */ 202 #define PLAT_ARM_TZC_BASE UL(0x2a4a0000) 203 #define PLAT_ARM_TZC_NS_DEV_ACCESS ( \ 204 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CCI400) | \ 205 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_PCIE) | \ 206 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD0) | \ 207 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD1) | \ 208 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_USB) | \ 209 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_DMA330) | \ 210 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_THINLINKS) | \ 211 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_AP) | \ 212 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_GPU) | \ 213 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CORESIGHT)) 214 215 /* 216 * Required ARM CSS based platform porting definitions 217 */ 218 219 /* GIC related constants (no GICR in GIC-400) */ 220 #define PLAT_ARM_GICD_BASE UL(0x2c010000) 221 #define PLAT_ARM_GICC_BASE UL(0x2c02f000) 222 #define PLAT_ARM_GICH_BASE UL(0x2c04f000) 223 #define PLAT_ARM_GICV_BASE UL(0x2c06f000) 224 225 /* MHU related constants */ 226 #define PLAT_CSS_MHU_BASE UL(0x2b1f0000) 227 #define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE 228 229 /* 230 * Base address of the first memory region used for communication between AP 231 * and SCP. Used by the BOM and SCPI protocols. 232 */ 233 #if !CSS_USE_SCMI_SDS_DRIVER 234 /* 235 * Note that this is located at the same address as SCP_BOOT_CFG_ADDR, which 236 * means the SCP/AP configuration data gets overwritten when the AP initiates 237 * communication with the SCP. The configuration data is expected to be a 238 * 32-bit word on all CSS platforms. On Juno, part of this configuration is 239 * which CPU is the primary, according to the shift and mask definitions below. 240 */ 241 #define PLAT_CSS_SCP_COM_SHARED_MEM_BASE (ARM_TRUSTED_SRAM_BASE + UL(0x80)) 242 #define PLAT_CSS_PRIMARY_CPU_SHIFT 8 243 #define PLAT_CSS_PRIMARY_CPU_BIT_WIDTH 4 244 #endif 245 246 /* 247 * PLAT_CSS_MAX_SCP_BL2_SIZE is calculated using the current 248 * SCP_BL2 size plus a little space for growth. 249 */ 250 #define PLAT_CSS_MAX_SCP_BL2_SIZE UL(0x14000) 251 252 /* 253 * PLAT_CSS_MAX_SCP_BL2U_SIZE is calculated using the current 254 * SCP_BL2U size plus a little space for growth. 255 */ 256 #define PLAT_CSS_MAX_SCP_BL2U_SIZE UL(0x14000) 257 258 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 259 CSS_G1S_IRQ_PROPS(grp), \ 260 ARM_G1S_IRQ_PROPS(grp), \ 261 INTR_PROP_DESC(JUNO_IRQ_DMA_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 262 (grp), GIC_INTR_CFG_LEVEL), \ 263 INTR_PROP_DESC(JUNO_IRQ_HDLCD0_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 264 (grp), GIC_INTR_CFG_LEVEL), \ 265 INTR_PROP_DESC(JUNO_IRQ_HDLCD1_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 266 (grp), GIC_INTR_CFG_LEVEL), \ 267 INTR_PROP_DESC(JUNO_IRQ_USB_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 268 (grp), GIC_INTR_CFG_LEVEL), \ 269 INTR_PROP_DESC(JUNO_IRQ_THIN_LINKS_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 270 (grp), GIC_INTR_CFG_LEVEL), \ 271 INTR_PROP_DESC(JUNO_IRQ_SEC_I2C, GIC_HIGHEST_SEC_PRIORITY, \ 272 (grp), GIC_INTR_CFG_LEVEL), \ 273 INTR_PROP_DESC(JUNO_IRQ_GPU_SMMU_1, GIC_HIGHEST_SEC_PRIORITY, \ 274 (grp), GIC_INTR_CFG_LEVEL), \ 275 INTR_PROP_DESC(JUNO_IRQ_ETR_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 276 (grp), GIC_INTR_CFG_LEVEL) 277 278 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) 279 280 /* 281 * Required ARM CSS SoC based platform porting definitions 282 */ 283 284 /* CSS SoC NIC-400 Global Programmers View (GPV) */ 285 #define PLAT_SOC_CSS_NIC400_BASE UL(0x2a000000) 286 287 #define PLAT_ARM_PRIVATE_SDEI_EVENTS ARM_SDEI_PRIVATE_EVENTS 288 #define PLAT_ARM_SHARED_SDEI_EVENTS ARM_SDEI_SHARED_EVENTS 289 290 /* System power domain level */ 291 #define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2 292 293 /* 294 * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes 295 */ 296 #ifdef __aarch64__ 297 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) 298 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) 299 #else 300 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 301 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 302 #endif 303 304 #endif /* PLATFORM_DEF_H */ 305