1 /* 2 * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __PLATFORM_DEF_H__ 8 #define __PLATFORM_DEF_H__ 9 10 #include <arm_def.h> 11 #include <board_arm_def.h> 12 #include <board_css_def.h> 13 #include <common_def.h> 14 #include <css_def.h> 15 #include <soc_css_def.h> 16 #include <tzc400.h> 17 #include <v2m_def.h> 18 #include "../juno_def.h" 19 20 /* Required platform porting definitions */ 21 /* Juno supports system power domain */ 22 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL2 23 #define PLAT_NUM_PWR_DOMAINS (ARM_SYSTEM_COUNT + \ 24 JUNO_CLUSTER_COUNT + \ 25 PLATFORM_CORE_COUNT) 26 #define PLATFORM_CORE_COUNT (JUNO_CLUSTER0_CORE_COUNT + \ 27 JUNO_CLUSTER1_CORE_COUNT) 28 29 /* 30 * Other platform porting definitions are provided by included headers 31 */ 32 33 /* 34 * Required ARM standard platform porting definitions 35 */ 36 #define PLAT_ARM_CLUSTER_COUNT JUNO_CLUSTER_COUNT 37 38 /* Use the bypass address */ 39 #define PLAT_ARM_TRUSTED_ROM_BASE V2M_FLASH0_BASE + BL1_ROM_BYPASS_OFFSET 40 41 /* 42 * Actual ROM size on Juno is 64 KB, but TBB currently requires at least 80 KB 43 * in debug mode. We can test TBB on Juno bypassing the ROM and using 128 KB of 44 * flash 45 */ 46 #if TRUSTED_BOARD_BOOT 47 #define PLAT_ARM_TRUSTED_ROM_SIZE 0x00020000 48 #else 49 #define PLAT_ARM_TRUSTED_ROM_SIZE 0x00010000 50 #endif /* TRUSTED_BOARD_BOOT */ 51 52 /* 53 * If ARM_BOARD_OPTIMISE_MEM=0 then Juno uses the default, unoptimised values 54 * defined for ARM development platforms. 55 */ 56 #if ARM_BOARD_OPTIMISE_MEM 57 /* 58 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the 59 * plat_arm_mmap array defined for each BL stage. 60 */ 61 #ifdef IMAGE_BL1 62 # define PLAT_ARM_MMAP_ENTRIES 7 63 # define MAX_XLAT_TABLES 4 64 #endif 65 66 #ifdef IMAGE_BL2 67 # define PLAT_ARM_MMAP_ENTRIES 8 68 # define MAX_XLAT_TABLES 3 69 #endif 70 71 #ifdef IMAGE_BL2U 72 # define PLAT_ARM_MMAP_ENTRIES 4 73 # define MAX_XLAT_TABLES 3 74 #endif 75 76 #ifdef IMAGE_BL31 77 # define PLAT_ARM_MMAP_ENTRIES 5 78 # define MAX_XLAT_TABLES 2 79 #endif 80 81 #ifdef IMAGE_BL32 82 # define PLAT_ARM_MMAP_ENTRIES 5 83 # define MAX_XLAT_TABLES 4 84 #endif 85 86 /* 87 * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size 88 * plus a little space for growth. 89 */ 90 #if TRUSTED_BOARD_BOOT 91 # define PLAT_ARM_MAX_BL1_RW_SIZE 0x9000 92 #else 93 # define PLAT_ARM_MAX_BL1_RW_SIZE 0x6000 94 #endif 95 96 /* 97 * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a 98 * little space for growth. 99 */ 100 #if TRUSTED_BOARD_BOOT 101 # define PLAT_ARM_MAX_BL2_SIZE 0x1D000 102 #else 103 # define PLAT_ARM_MAX_BL2_SIZE 0xC000 104 #endif 105 106 /* 107 * PLAT_ARM_MAX_BL31_SIZE is calculated using the current BL31 debug size plus a 108 * little space for growth. 109 */ 110 #define PLAT_ARM_MAX_BL31_SIZE 0x1D000 111 112 #endif /* ARM_BOARD_OPTIMISE_MEM */ 113 114 /* CCI related constants */ 115 #define PLAT_ARM_CCI_BASE 0x2c090000 116 #define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 4 117 #define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 3 118 119 /* System timer related constants */ 120 #define PLAT_ARM_NSTIMER_FRAME_ID 1 121 122 /* TZC related constants */ 123 #define PLAT_ARM_TZC_BASE 0x2a4a0000 124 #define PLAT_ARM_TZC_NS_DEV_ACCESS ( \ 125 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CCI400) | \ 126 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_PCIE) | \ 127 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD0) | \ 128 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD1) | \ 129 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_USB) | \ 130 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_DMA330) | \ 131 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_THINLINKS) | \ 132 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_AP) | \ 133 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_GPU) | \ 134 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CORESIGHT)) 135 136 /* 137 * Required ARM CSS based platform porting definitions 138 */ 139 140 /* GIC related constants (no GICR in GIC-400) */ 141 #define PLAT_ARM_GICD_BASE 0x2c010000 142 #define PLAT_ARM_GICC_BASE 0x2c02f000 143 #define PLAT_ARM_GICH_BASE 0x2c04f000 144 #define PLAT_ARM_GICV_BASE 0x2c06f000 145 146 /* MHU related constants */ 147 #define PLAT_CSS_MHU_BASE 0x2b1f0000 148 149 /* 150 * Base address of the first memory region used for communication between AP 151 * and SCP. Used by the BOM and SCPI protocols. 152 * 153 * Note that this is located at the same address as SCP_BOOT_CFG_ADDR, which 154 * means the SCP/AP configuration data gets overwritten when the AP initiates 155 * communication with the SCP. The configuration data is expected to be a 156 * 32-bit word on all CSS platforms. On Juno, part of this configuration is 157 * which CPU is the primary, according to the shift and mask definitions below. 158 */ 159 #define PLAT_CSS_SCP_COM_SHARED_MEM_BASE (ARM_TRUSTED_SRAM_BASE + 0x80) 160 #define PLAT_CSS_PRIMARY_CPU_SHIFT 8 161 #define PLAT_CSS_PRIMARY_CPU_BIT_WIDTH 4 162 163 /* 164 * PLAT_CSS_MAX_SCP_BL2_SIZE is calculated using the current 165 * SCP_BL2 size plus a little space for growth. 166 */ 167 #define PLAT_CSS_MAX_SCP_BL2_SIZE 0x1D000 168 169 /* 170 * PLAT_CSS_MAX_SCP_BL2U_SIZE is calculated using the current 171 * SCP_BL2U size plus a little space for growth. 172 */ 173 #define PLAT_CSS_MAX_SCP_BL2U_SIZE 0x1D000 174 175 /* 176 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 177 * terminology. On a GICv2 system or mode, the lists will be merged and treated 178 * as Group 0 interrupts. 179 */ 180 #define PLAT_ARM_G1S_IRQS CSS_G1S_IRQS, \ 181 ARM_G1S_IRQS, \ 182 JUNO_IRQ_DMA_SMMU, \ 183 JUNO_IRQ_HDLCD0_SMMU, \ 184 JUNO_IRQ_HDLCD1_SMMU, \ 185 JUNO_IRQ_USB_SMMU, \ 186 JUNO_IRQ_THIN_LINKS_SMMU, \ 187 JUNO_IRQ_SEC_I2C, \ 188 JUNO_IRQ_GPU_SMMU_1, \ 189 JUNO_IRQ_ETR_SMMU 190 191 #define PLAT_ARM_G0_IRQS ARM_G0_IRQS 192 193 /* 194 * Required ARM CSS SoC based platform porting definitions 195 */ 196 197 /* CSS SoC NIC-400 Global Programmers View (GPV) */ 198 #define PLAT_SOC_CSS_NIC400_BASE 0x2a000000 199 200 #endif /* __PLATFORM_DEF_H__ */ 201