1 /* 2 * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __PLATFORM_DEF_H__ 8 #define __PLATFORM_DEF_H__ 9 10 /* Enable the dynamic translation tables library. */ 11 #ifdef AARCH32 12 # if defined(IMAGE_BL32) && RESET_TO_SP_MIN 13 # define PLAT_XLAT_TABLES_DYNAMIC 1 14 # endif 15 #else 16 # if defined(IMAGE_BL31) && RESET_TO_BL31 17 # define PLAT_XLAT_TABLES_DYNAMIC 1 18 # endif 19 #endif /* AARCH32 */ 20 21 22 #include <arm_def.h> 23 #include <board_arm_def.h> 24 #include <board_css_def.h> 25 #include <common_def.h> 26 #include <css_def.h> 27 #if TRUSTED_BOARD_BOOT 28 #include <mbedtls_config.h> 29 #endif 30 #include <soc_css_def.h> 31 #include <tzc400.h> 32 #include <v2m_def.h> 33 #include "../juno_def.h" 34 35 /* Required platform porting definitions */ 36 /* Juno supports system power domain */ 37 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL2 38 #define PLAT_NUM_PWR_DOMAINS (ARM_SYSTEM_COUNT + \ 39 JUNO_CLUSTER_COUNT + \ 40 PLATFORM_CORE_COUNT) 41 #define PLATFORM_CORE_COUNT (JUNO_CLUSTER0_CORE_COUNT + \ 42 JUNO_CLUSTER1_CORE_COUNT) 43 44 /* Cryptocell HW Base address */ 45 #define PLAT_CRYPTOCELL_BASE 0x60050000 46 47 /* 48 * Other platform porting definitions are provided by included headers 49 */ 50 51 /* 52 * Required ARM standard platform porting definitions 53 */ 54 #define PLAT_ARM_CLUSTER_COUNT JUNO_CLUSTER_COUNT 55 56 /* Use the bypass address */ 57 #define PLAT_ARM_TRUSTED_ROM_BASE V2M_FLASH0_BASE + BL1_ROM_BYPASS_OFFSET 58 59 #define NSRAM_BASE 0x2e000000 60 #define NSRAM_SIZE 0x00008000 /* 32KB */ 61 62 /* virtual address used by dynamic mem_protect for chunk_base */ 63 #define PLAT_ARM_MEM_PROTEC_VA_FRAME 0xc0000000 64 65 /* 66 * Actual ROM size on Juno is 64 KB, but TBB currently requires at least 80 KB 67 * in debug mode. We can test TBB on Juno bypassing the ROM and using 128 KB of 68 * flash 69 */ 70 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE 0 71 72 #if TRUSTED_BOARD_BOOT 73 #define PLAT_ARM_TRUSTED_ROM_SIZE 0x00020000 74 #else 75 #define PLAT_ARM_TRUSTED_ROM_SIZE 0x00010000 76 #endif /* TRUSTED_BOARD_BOOT */ 77 78 /* 79 * If ARM_BOARD_OPTIMISE_MEM=0 then Juno uses the default, unoptimised values 80 * defined for ARM development platforms. 81 */ 82 #if ARM_BOARD_OPTIMISE_MEM 83 /* 84 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the 85 * plat_arm_mmap array defined for each BL stage. 86 */ 87 #ifdef IMAGE_BL1 88 # define PLAT_ARM_MMAP_ENTRIES 7 89 # define MAX_XLAT_TABLES 4 90 #endif 91 92 #ifdef IMAGE_BL2 93 #ifdef SPD_opteed 94 # define PLAT_ARM_MMAP_ENTRIES 11 95 # define MAX_XLAT_TABLES 5 96 #else 97 # define PLAT_ARM_MMAP_ENTRIES 10 98 # define MAX_XLAT_TABLES 4 99 #endif 100 #endif 101 102 #ifdef IMAGE_BL2U 103 # define PLAT_ARM_MMAP_ENTRIES 5 104 # define MAX_XLAT_TABLES 3 105 #endif 106 107 #ifdef IMAGE_BL31 108 # define PLAT_ARM_MMAP_ENTRIES 7 109 # define MAX_XLAT_TABLES 3 110 #endif 111 112 #ifdef IMAGE_BL32 113 # define PLAT_ARM_MMAP_ENTRIES 6 114 # define MAX_XLAT_TABLES 4 115 #endif 116 117 /* 118 * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size 119 * plus a little space for growth. 120 */ 121 #if TRUSTED_BOARD_BOOT 122 # define PLAT_ARM_MAX_BL1_RW_SIZE 0xB000 123 #else 124 # define PLAT_ARM_MAX_BL1_RW_SIZE 0x6000 125 #endif 126 127 /* 128 * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page 129 */ 130 #if USE_ROMLIB 131 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE 0x1000 132 #else 133 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE 0 134 #endif 135 136 /* 137 * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a 138 * little space for growth. 139 */ 140 #if TRUSTED_BOARD_BOOT 141 #if TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA 142 # define PLAT_ARM_MAX_BL2_SIZE 0x1F000 143 #elif TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_ECDSA 144 # define PLAT_ARM_MAX_BL2_SIZE 0x1D000 145 #else 146 # define PLAT_ARM_MAX_BL2_SIZE 0x1C000 147 #endif 148 #else 149 # define PLAT_ARM_MAX_BL2_SIZE 0xE000 150 #endif 151 152 /* 153 * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is 154 * calculated using the current BL31 PROGBITS debug size plus the sizes of 155 * BL2 and BL1-RW. SCP_BL2 image is loaded into the space BL31 -> BL2_BASE. 156 * Hence the BL31 PROGBITS size should be >= PLAT_CSS_MAX_SCP_BL2_SIZE. 157 */ 158 #define PLAT_ARM_MAX_BL31_SIZE 0x3E000 159 160 #if JUNO_AARCH32_EL3_RUNTIME 161 /* 162 * Since BL32 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL32_SIZE is 163 * calculated using the current BL32 PROGBITS debug size plus the sizes of 164 * BL2 and BL1-RW. SCP_BL2 image is loaded into the space BL32 -> BL2_BASE. 165 * Hence the BL32 PROGBITS size should be >= PLAT_CSS_MAX_SCP_BL2_SIZE. 166 */ 167 #define PLAT_ARM_MAX_BL32_SIZE 0x3E000 168 #endif 169 170 /* 171 * Since free SRAM space is scant, enable the ASSERTION message size 172 * optimization by fixing the PLAT_LOG_LEVEL_ASSERT to LOG_LEVEL_INFO (40). 173 */ 174 #define PLAT_LOG_LEVEL_ASSERT 40 175 176 #endif /* ARM_BOARD_OPTIMISE_MEM */ 177 178 /* CCI related constants */ 179 #define PLAT_ARM_CCI_BASE 0x2c090000 180 #define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 4 181 #define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 3 182 183 /* System timer related constants */ 184 #define PLAT_ARM_NSTIMER_FRAME_ID 1 185 186 /* TZC related constants */ 187 #define PLAT_ARM_TZC_BASE 0x2a4a0000 188 #define PLAT_ARM_TZC_NS_DEV_ACCESS ( \ 189 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CCI400) | \ 190 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_PCIE) | \ 191 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD0) | \ 192 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD1) | \ 193 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_USB) | \ 194 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_DMA330) | \ 195 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_THINLINKS) | \ 196 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_AP) | \ 197 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_GPU) | \ 198 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CORESIGHT)) 199 200 /* 201 * Required ARM CSS based platform porting definitions 202 */ 203 204 /* GIC related constants (no GICR in GIC-400) */ 205 #define PLAT_ARM_GICD_BASE 0x2c010000 206 #define PLAT_ARM_GICC_BASE 0x2c02f000 207 #define PLAT_ARM_GICH_BASE 0x2c04f000 208 #define PLAT_ARM_GICV_BASE 0x2c06f000 209 210 /* MHU related constants */ 211 #define PLAT_CSS_MHU_BASE 0x2b1f0000 212 213 /* 214 * Base address of the first memory region used for communication between AP 215 * and SCP. Used by the BOM and SCPI protocols. 216 */ 217 #if !CSS_USE_SCMI_SDS_DRIVER 218 /* 219 * Note that this is located at the same address as SCP_BOOT_CFG_ADDR, which 220 * means the SCP/AP configuration data gets overwritten when the AP initiates 221 * communication with the SCP. The configuration data is expected to be a 222 * 32-bit word on all CSS platforms. On Juno, part of this configuration is 223 * which CPU is the primary, according to the shift and mask definitions below. 224 */ 225 #define PLAT_CSS_SCP_COM_SHARED_MEM_BASE (ARM_TRUSTED_SRAM_BASE + 0x80) 226 #define PLAT_CSS_PRIMARY_CPU_SHIFT 8 227 #define PLAT_CSS_PRIMARY_CPU_BIT_WIDTH 4 228 #endif 229 230 /* 231 * PLAT_CSS_MAX_SCP_BL2_SIZE is calculated using the current 232 * SCP_BL2 size plus a little space for growth. 233 */ 234 #define PLAT_CSS_MAX_SCP_BL2_SIZE 0x14000 235 236 /* 237 * PLAT_CSS_MAX_SCP_BL2U_SIZE is calculated using the current 238 * SCP_BL2U size plus a little space for growth. 239 */ 240 #define PLAT_CSS_MAX_SCP_BL2U_SIZE 0x14000 241 242 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 243 CSS_G1S_IRQ_PROPS(grp), \ 244 ARM_G1S_IRQ_PROPS(grp), \ 245 INTR_PROP_DESC(JUNO_IRQ_DMA_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 246 grp, GIC_INTR_CFG_LEVEL), \ 247 INTR_PROP_DESC(JUNO_IRQ_HDLCD0_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 248 grp, GIC_INTR_CFG_LEVEL), \ 249 INTR_PROP_DESC(JUNO_IRQ_HDLCD1_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 250 grp, GIC_INTR_CFG_LEVEL), \ 251 INTR_PROP_DESC(JUNO_IRQ_USB_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 252 grp, GIC_INTR_CFG_LEVEL), \ 253 INTR_PROP_DESC(JUNO_IRQ_THIN_LINKS_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 254 grp, GIC_INTR_CFG_LEVEL), \ 255 INTR_PROP_DESC(JUNO_IRQ_SEC_I2C, GIC_HIGHEST_SEC_PRIORITY, \ 256 grp, GIC_INTR_CFG_LEVEL), \ 257 INTR_PROP_DESC(JUNO_IRQ_GPU_SMMU_1, GIC_HIGHEST_SEC_PRIORITY, \ 258 grp, GIC_INTR_CFG_LEVEL), \ 259 INTR_PROP_DESC(JUNO_IRQ_ETR_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 260 grp, GIC_INTR_CFG_LEVEL) 261 262 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) 263 264 /* 265 * Required ARM CSS SoC based platform porting definitions 266 */ 267 268 /* CSS SoC NIC-400 Global Programmers View (GPV) */ 269 #define PLAT_SOC_CSS_NIC400_BASE 0x2a000000 270 271 #define PLAT_ARM_PRIVATE_SDEI_EVENTS ARM_SDEI_PRIVATE_EVENTS 272 #define PLAT_ARM_SHARED_SDEI_EVENTS ARM_SDEI_SHARED_EVENTS 273 274 #endif /* __PLATFORM_DEF_H__ */ 275