1/* 2 * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31#include <arch.h> 32#include <asm_macros.S> 33#include <bl_common.h> 34#include <cortex_a53.h> 35#include <cortex_a57.h> 36#include <cortex_a72.h> 37#include <v2m_def.h> 38#include "../juno_def.h" 39 40 41 .globl plat_reset_handler 42 .globl plat_arm_calc_core_pos 43 44#define JUNO_REVISION(rev) REV_JUNO_R##rev 45#define JUNO_HANDLER(rev) plat_reset_handler_juno_r##rev 46#define JUMP_TO_HANDLER_IF_JUNO_R(revision) \ 47 jump_to_handler JUNO_REVISION(revision), JUNO_HANDLER(revision) 48 49 /* -------------------------------------------------------------------- 50 * Helper macro to jump to the given handler if the board revision 51 * matches. 52 * Expects the Juno board revision in x0. 53 * -------------------------------------------------------------------- 54 */ 55 .macro jump_to_handler _revision, _handler 56 cmp x0, #\_revision 57 b.eq \_handler 58 .endm 59 60 /* -------------------------------------------------------------------- 61 * Helper macro that reads the part number of the current CPU and jumps 62 * to the given label if it matches the CPU MIDR provided. 63 * 64 * Clobbers x0. 65 * -------------------------------------------------------------------- 66 */ 67 .macro jump_if_cpu_midr _cpu_midr, _label 68 mrs x0, midr_el1 69 ubfx x0, x0, MIDR_PN_SHIFT, #12 70 cmp w0, #((\_cpu_midr >> MIDR_PN_SHIFT) & MIDR_PN_MASK) 71 b.eq \_label 72 .endm 73 74 /* -------------------------------------------------------------------- 75 * Platform reset handler for Juno R0. 76 * 77 * Juno R0 has the following topology: 78 * - Quad core Cortex-A53 processor cluster; 79 * - Dual core Cortex-A57 processor cluster. 80 * 81 * This handler does the following: 82 * - Implement workaround for defect id 831273 by enabling an event 83 * stream every 65536 cycles. 84 * - Set the L2 Data RAM latency to 2 (i.e. 3 cycles) for Cortex-A57 85 * - Set the L2 Tag RAM latency to 2 (i.e. 3 cycles) for Cortex-A57 86 * -------------------------------------------------------------------- 87 */ 88func JUNO_HANDLER(0) 89 /* -------------------------------------------------------------------- 90 * Enable the event stream every 65536 cycles 91 * -------------------------------------------------------------------- 92 */ 93 mov x0, #(0xf << EVNTI_SHIFT) 94 orr x0, x0, #EVNTEN_BIT 95 msr CNTKCTL_EL1, x0 96 97 /* -------------------------------------------------------------------- 98 * Nothing else to do on Cortex-A53. 99 * -------------------------------------------------------------------- 100 */ 101 jump_if_cpu_midr CORTEX_A53_MIDR, 1f 102 103 /* -------------------------------------------------------------------- 104 * Cortex-A57 specific settings 105 * -------------------------------------------------------------------- 106 */ 107 mov x0, #((L2_DATA_RAM_LATENCY_3_CYCLES << L2CTLR_DATA_RAM_LATENCY_SHIFT) | \ 108 (L2_TAG_RAM_LATENCY_3_CYCLES << L2CTLR_TAG_RAM_LATENCY_SHIFT)) 109 msr L2CTLR_EL1, x0 1101: 111 isb 112 ret 113endfunc JUNO_HANDLER(0) 114 115 /* -------------------------------------------------------------------- 116 * Platform reset handler for Juno R1. 117 * 118 * Juno R1 has the following topology: 119 * - Quad core Cortex-A53 processor cluster; 120 * - Dual core Cortex-A57 processor cluster. 121 * 122 * This handler does the following: 123 * - Set the L2 Data RAM latency to 2 (i.e. 3 cycles) for Cortex-A57 124 * 125 * Note that: 126 * - The default value for the L2 Tag RAM latency for Cortex-A57 is 127 * suitable. 128 * - Defect #831273 doesn't affect Juno R1. 129 * -------------------------------------------------------------------- 130 */ 131func JUNO_HANDLER(1) 132 /* -------------------------------------------------------------------- 133 * Nothing to do on Cortex-A53. 134 * -------------------------------------------------------------------- 135 */ 136 jump_if_cpu_midr CORTEX_A57_MIDR, A57 137 ret 138 139A57: 140 /* -------------------------------------------------------------------- 141 * Cortex-A57 specific settings 142 * -------------------------------------------------------------------- 143 */ 144 mov x0, #(L2_DATA_RAM_LATENCY_3_CYCLES << L2CTLR_DATA_RAM_LATENCY_SHIFT) 145 msr L2CTLR_EL1, x0 146 isb 147 ret 148endfunc JUNO_HANDLER(1) 149 150 /* -------------------------------------------------------------------- 151 * Platform reset handler for Juno R2. 152 * 153 * Juno R2 has the following topology: 154 * - Quad core Cortex-A53 processor cluster; 155 * - Dual core Cortex-A72 processor cluster. 156 * 157 * This handler does the following: 158 * - Set the L2 Data RAM latency to 2 (i.e. 3 cycles) for Cortex-A72 159 * - Set the L2 Tag RAM latency to 1 (i.e. 2 cycles) for Cortex-A72 160 * 161 * Note that: 162 * - Defect #831273 doesn't affect Juno R2. 163 * -------------------------------------------------------------------- 164 */ 165func JUNO_HANDLER(2) 166 /* -------------------------------------------------------------------- 167 * Nothing to do on Cortex-A53. 168 * -------------------------------------------------------------------- 169 */ 170 jump_if_cpu_midr CORTEX_A72_MIDR, A72 171 ret 172 173A72: 174 /* -------------------------------------------------------------------- 175 * Cortex-A72 specific settings 176 * -------------------------------------------------------------------- 177 */ 178 mov x0, #((L2_DATA_RAM_LATENCY_3_CYCLES << L2CTLR_DATA_RAM_LATENCY_SHIFT) | \ 179 (L2_TAG_RAM_LATENCY_2_CYCLES << L2CTLR_TAG_RAM_LATENCY_SHIFT)) 180 msr L2CTLR_EL1, x0 181 isb 182 ret 183endfunc JUNO_HANDLER(2) 184 185 /* -------------------------------------------------------------------- 186 * void plat_reset_handler(void); 187 * 188 * Determine the Juno board revision and call the appropriate reset 189 * handler. 190 * -------------------------------------------------------------------- 191 */ 192func plat_reset_handler 193 /* Read the V2M SYS_ID register */ 194 mov_imm x0, (V2M_SYSREGS_BASE + V2M_SYS_ID) 195 ldr w1, [x0] 196 /* Extract board revision from the SYS_ID */ 197 ubfx x0, x1, #V2M_SYS_ID_REV_SHIFT, #4 198 199 JUMP_TO_HANDLER_IF_JUNO_R(0) 200 JUMP_TO_HANDLER_IF_JUNO_R(1) 201 JUMP_TO_HANDLER_IF_JUNO_R(2) 202 203 /* Board revision is not supported */ 204 no_ret plat_panic_handler 205 206endfunc plat_reset_handler 207 208 /* ----------------------------------------------------- 209 * unsigned int plat_arm_calc_core_pos(u_register_t mpidr) 210 * Helper function to calculate the core position. 211 * ----------------------------------------------------- 212 */ 213func plat_arm_calc_core_pos 214 b css_calc_core_pos_swap_cluster 215endfunc plat_arm_calc_core_pos 216