xref: /rk3399_ARM-atf/plat/arm/board/juno/aarch32/juno_helpers.S (revision 6f249345e2aa2343ce67222e82dafc539e973ec5)
1*6f249345SYatharth Kochar/*
2*6f249345SYatharth Kochar * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
3*6f249345SYatharth Kochar *
4*6f249345SYatharth Kochar * Redistribution and use in source and binary forms, with or without
5*6f249345SYatharth Kochar * modification, are permitted provided that the following conditions are met:
6*6f249345SYatharth Kochar *
7*6f249345SYatharth Kochar * Redistributions of source code must retain the above copyright notice, this
8*6f249345SYatharth Kochar * list of conditions and the following disclaimer.
9*6f249345SYatharth Kochar *
10*6f249345SYatharth Kochar * Redistributions in binary form must reproduce the above copyright notice,
11*6f249345SYatharth Kochar * this list of conditions and the following disclaimer in the documentation
12*6f249345SYatharth Kochar * and/or other materials provided with the distribution.
13*6f249345SYatharth Kochar *
14*6f249345SYatharth Kochar * Neither the name of ARM nor the names of its contributors may be used
15*6f249345SYatharth Kochar * to endorse or promote products derived from this software without specific
16*6f249345SYatharth Kochar * prior written permission.
17*6f249345SYatharth Kochar *
18*6f249345SYatharth Kochar * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19*6f249345SYatharth Kochar * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20*6f249345SYatharth Kochar * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21*6f249345SYatharth Kochar * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22*6f249345SYatharth Kochar * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23*6f249345SYatharth Kochar * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24*6f249345SYatharth Kochar * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25*6f249345SYatharth Kochar * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26*6f249345SYatharth Kochar * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27*6f249345SYatharth Kochar * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28*6f249345SYatharth Kochar * POSSIBILITY OF SUCH DAMAGE.
29*6f249345SYatharth Kochar */
30*6f249345SYatharth Kochar
31*6f249345SYatharth Kochar#include <arch.h>
32*6f249345SYatharth Kochar#include <asm_macros.S>
33*6f249345SYatharth Kochar#include <bl_common.h>
34*6f249345SYatharth Kochar#include <cortex_a53.h>
35*6f249345SYatharth Kochar#include <cortex_a57.h>
36*6f249345SYatharth Kochar#include <cortex_a72.h>
37*6f249345SYatharth Kochar#include <v2m_def.h>
38*6f249345SYatharth Kochar#include "../juno_def.h"
39*6f249345SYatharth Kochar
40*6f249345SYatharth Kochar
41*6f249345SYatharth Kochar	.globl	plat_reset_handler
42*6f249345SYatharth Kochar	.globl	plat_arm_calc_core_pos
43*6f249345SYatharth Kochar
44*6f249345SYatharth Kochar#define JUNO_REVISION(rev)	REV_JUNO_R##rev
45*6f249345SYatharth Kochar#define JUNO_HANDLER(rev)	plat_reset_handler_juno_r##rev
46*6f249345SYatharth Kochar#define JUMP_TO_HANDLER_IF_JUNO_R(revision)	\
47*6f249345SYatharth Kochar	jump_to_handler JUNO_REVISION(revision), JUNO_HANDLER(revision)
48*6f249345SYatharth Kochar
49*6f249345SYatharth Kochar	/* --------------------------------------------------------------------
50*6f249345SYatharth Kochar	 * Helper macro to jump to the given handler if the board revision
51*6f249345SYatharth Kochar	 * matches.
52*6f249345SYatharth Kochar	 * Expects the Juno board revision in x0.
53*6f249345SYatharth Kochar	 * --------------------------------------------------------------------
54*6f249345SYatharth Kochar	 */
55*6f249345SYatharth Kochar	.macro jump_to_handler _revision, _handler
56*6f249345SYatharth Kochar	cmp	r0, #\_revision
57*6f249345SYatharth Kochar	beq	\_handler
58*6f249345SYatharth Kochar	.endm
59*6f249345SYatharth Kochar
60*6f249345SYatharth Kochar	/* --------------------------------------------------------------------
61*6f249345SYatharth Kochar	 * Helper macro that reads the part number of the current CPU and jumps
62*6f249345SYatharth Kochar	 * to the given label if it matches the CPU MIDR provided.
63*6f249345SYatharth Kochar	 *
64*6f249345SYatharth Kochar	 * Clobbers r0.
65*6f249345SYatharth Kochar	 * --------------------------------------------------------------------
66*6f249345SYatharth Kochar	 */
67*6f249345SYatharth Kochar	.macro  jump_if_cpu_midr _cpu_midr, _label
68*6f249345SYatharth Kochar	ldcopr	r0, MIDR
69*6f249345SYatharth Kochar	ubfx	r0, r0, #MIDR_PN_SHIFT, #12
70*6f249345SYatharth Kochar	ldr	r1, =((\_cpu_midr >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
71*6f249345SYatharth Kochar	cmp	r0, r1
72*6f249345SYatharth Kochar	beq	\_label
73*6f249345SYatharth Kochar	.endm
74*6f249345SYatharth Kochar
75*6f249345SYatharth Kochar	/* --------------------------------------------------------------------
76*6f249345SYatharth Kochar	 * Platform reset handler for Juno R0.
77*6f249345SYatharth Kochar	 *
78*6f249345SYatharth Kochar	 * Juno R0 has the following topology:
79*6f249345SYatharth Kochar	 * - Quad core Cortex-A53 processor cluster;
80*6f249345SYatharth Kochar	 * - Dual core Cortex-A57 processor cluster.
81*6f249345SYatharth Kochar	 *
82*6f249345SYatharth Kochar	 * This handler does the following:
83*6f249345SYatharth Kochar	 * - Implement workaround for defect id 831273 by enabling an event
84*6f249345SYatharth Kochar	 *   stream every 65536 cycles.
85*6f249345SYatharth Kochar	 * - Set the L2 Data RAM latency to 2 (i.e. 3 cycles) for Cortex-A57
86*6f249345SYatharth Kochar	 * - Set the L2 Tag RAM latency to 2 (i.e. 3 cycles) for Cortex-A57
87*6f249345SYatharth Kochar	 * --------------------------------------------------------------------
88*6f249345SYatharth Kochar	 */
89*6f249345SYatharth Kocharfunc JUNO_HANDLER(0)
90*6f249345SYatharth Kochar	/* --------------------------------------------------------------------
91*6f249345SYatharth Kochar	 * Enable the event stream every 65536 cycles
92*6f249345SYatharth Kochar	 * --------------------------------------------------------------------
93*6f249345SYatharth Kochar	 */
94*6f249345SYatharth Kochar	mov	r0, #(0xf << EVNTI_SHIFT)
95*6f249345SYatharth Kochar	orr	r0, r0, #EVNTEN_BIT
96*6f249345SYatharth Kochar	stcopr	r0, CNTKCTL
97*6f249345SYatharth Kochar
98*6f249345SYatharth Kochar	/* --------------------------------------------------------------------
99*6f249345SYatharth Kochar	 * Nothing else to do on Cortex-A53.
100*6f249345SYatharth Kochar	 * --------------------------------------------------------------------
101*6f249345SYatharth Kochar	 */
102*6f249345SYatharth Kochar	jump_if_cpu_midr CORTEX_A53_MIDR, 1f
103*6f249345SYatharth Kochar
104*6f249345SYatharth Kochar	/* --------------------------------------------------------------------
105*6f249345SYatharth Kochar	 * Cortex-A57 specific settings
106*6f249345SYatharth Kochar	 * --------------------------------------------------------------------
107*6f249345SYatharth Kochar	 */
108*6f249345SYatharth Kochar	mov	r0, #((L2_DATA_RAM_LATENCY_3_CYCLES << L2CTLR_DATA_RAM_LATENCY_SHIFT) |	\
109*6f249345SYatharth Kochar		      (L2_TAG_RAM_LATENCY_3_CYCLES << L2CTLR_TAG_RAM_LATENCY_SHIFT))
110*6f249345SYatharth Kochar	stcopr	r0, L2CTLR
111*6f249345SYatharth Kochar1:
112*6f249345SYatharth Kochar	isb
113*6f249345SYatharth Kochar	bx	lr
114*6f249345SYatharth Kocharendfunc JUNO_HANDLER(0)
115*6f249345SYatharth Kochar
116*6f249345SYatharth Kochar	/* --------------------------------------------------------------------
117*6f249345SYatharth Kochar	 * Platform reset handler for Juno R1.
118*6f249345SYatharth Kochar	 *
119*6f249345SYatharth Kochar	 * Juno R1 has the following topology:
120*6f249345SYatharth Kochar	 * - Quad core Cortex-A53 processor cluster;
121*6f249345SYatharth Kochar	 * - Dual core Cortex-A57 processor cluster.
122*6f249345SYatharth Kochar	 *
123*6f249345SYatharth Kochar	 * This handler does the following:
124*6f249345SYatharth Kochar	 * - Set the L2 Data RAM latency to 2 (i.e. 3 cycles) for Cortex-A57
125*6f249345SYatharth Kochar	 *
126*6f249345SYatharth Kochar	 * Note that:
127*6f249345SYatharth Kochar	 * - The default value for the L2 Tag RAM latency for Cortex-A57 is
128*6f249345SYatharth Kochar	 *   suitable.
129*6f249345SYatharth Kochar	 * - Defect #831273 doesn't affect Juno R1.
130*6f249345SYatharth Kochar	 * --------------------------------------------------------------------
131*6f249345SYatharth Kochar	 */
132*6f249345SYatharth Kocharfunc JUNO_HANDLER(1)
133*6f249345SYatharth Kochar	/* --------------------------------------------------------------------
134*6f249345SYatharth Kochar	 * Nothing to do on Cortex-A53.
135*6f249345SYatharth Kochar	 * --------------------------------------------------------------------
136*6f249345SYatharth Kochar	 */
137*6f249345SYatharth Kochar	jump_if_cpu_midr CORTEX_A57_MIDR, A57
138*6f249345SYatharth Kochar	bx	lr
139*6f249345SYatharth Kochar
140*6f249345SYatharth KocharA57:
141*6f249345SYatharth Kochar	/* --------------------------------------------------------------------
142*6f249345SYatharth Kochar	 * Cortex-A57 specific settings
143*6f249345SYatharth Kochar	 * --------------------------------------------------------------------
144*6f249345SYatharth Kochar	 */
145*6f249345SYatharth Kochar	mov	r0, #(L2_DATA_RAM_LATENCY_3_CYCLES << L2CTLR_DATA_RAM_LATENCY_SHIFT)
146*6f249345SYatharth Kochar	stcopr	r0, L2CTLR
147*6f249345SYatharth Kochar	isb
148*6f249345SYatharth Kochar	bx	lr
149*6f249345SYatharth Kocharendfunc JUNO_HANDLER(1)
150*6f249345SYatharth Kochar
151*6f249345SYatharth Kochar	/* --------------------------------------------------------------------
152*6f249345SYatharth Kochar	 * Platform reset handler for Juno R2.
153*6f249345SYatharth Kochar	 *
154*6f249345SYatharth Kochar	 * Juno R2 has the following topology:
155*6f249345SYatharth Kochar	 * - Quad core Cortex-A53 processor cluster;
156*6f249345SYatharth Kochar	 * - Dual core Cortex-A72 processor cluster.
157*6f249345SYatharth Kochar	 *
158*6f249345SYatharth Kochar	 * This handler does the following:
159*6f249345SYatharth Kochar	 * - Set the L2 Data RAM latency to 2 (i.e. 3 cycles) for Cortex-A72
160*6f249345SYatharth Kochar	 * - Set the L2 Tag RAM latency to 1 (i.e. 2 cycles) for Cortex-A72
161*6f249345SYatharth Kochar	 *
162*6f249345SYatharth Kochar	 * Note that:
163*6f249345SYatharth Kochar	 * - Defect #831273 doesn't affect Juno R2.
164*6f249345SYatharth Kochar	 * --------------------------------------------------------------------
165*6f249345SYatharth Kochar	 */
166*6f249345SYatharth Kocharfunc JUNO_HANDLER(2)
167*6f249345SYatharth Kochar	/* --------------------------------------------------------------------
168*6f249345SYatharth Kochar	 * Nothing to do on Cortex-A53.
169*6f249345SYatharth Kochar	 * --------------------------------------------------------------------
170*6f249345SYatharth Kochar	 */
171*6f249345SYatharth Kochar	jump_if_cpu_midr CORTEX_A72_MIDR, A72
172*6f249345SYatharth Kochar	bx	lr
173*6f249345SYatharth Kochar
174*6f249345SYatharth KocharA72:
175*6f249345SYatharth Kochar	/* --------------------------------------------------------------------
176*6f249345SYatharth Kochar	 * Cortex-A72 specific settings
177*6f249345SYatharth Kochar	 * --------------------------------------------------------------------
178*6f249345SYatharth Kochar	 */
179*6f249345SYatharth Kochar	mov	r0, #((L2_DATA_RAM_LATENCY_3_CYCLES << L2CTLR_DATA_RAM_LATENCY_SHIFT) |	\
180*6f249345SYatharth Kochar		      (L2_TAG_RAM_LATENCY_2_CYCLES << L2CTLR_TAG_RAM_LATENCY_SHIFT))
181*6f249345SYatharth Kochar	stcopr	r0, L2CTLR
182*6f249345SYatharth Kochar	isb
183*6f249345SYatharth Kochar	bx	lr
184*6f249345SYatharth Kocharendfunc JUNO_HANDLER(2)
185*6f249345SYatharth Kochar
186*6f249345SYatharth Kochar	/* --------------------------------------------------------------------
187*6f249345SYatharth Kochar	 * void plat_reset_handler(void);
188*6f249345SYatharth Kochar	 *
189*6f249345SYatharth Kochar	 * Determine the Juno board revision and call the appropriate reset
190*6f249345SYatharth Kochar	 * handler.
191*6f249345SYatharth Kochar	 * --------------------------------------------------------------------
192*6f249345SYatharth Kochar	 */
193*6f249345SYatharth Kocharfunc plat_reset_handler
194*6f249345SYatharth Kochar	/* Read the V2M SYS_ID register */
195*6f249345SYatharth Kochar	ldr	r0, =(V2M_SYSREGS_BASE + V2M_SYS_ID)
196*6f249345SYatharth Kochar	ldr	r1, [r0]
197*6f249345SYatharth Kochar	/* Extract board revision from the SYS_ID */
198*6f249345SYatharth Kochar	ubfx	r0, r1, #V2M_SYS_ID_REV_SHIFT, #4
199*6f249345SYatharth Kochar
200*6f249345SYatharth Kochar	JUMP_TO_HANDLER_IF_JUNO_R(0)
201*6f249345SYatharth Kochar	JUMP_TO_HANDLER_IF_JUNO_R(1)
202*6f249345SYatharth Kochar	JUMP_TO_HANDLER_IF_JUNO_R(2)
203*6f249345SYatharth Kochar
204*6f249345SYatharth Kochar	/* Board revision is not supported */
205*6f249345SYatharth Kochar	no_ret	plat_panic_handler
206*6f249345SYatharth Kochar
207*6f249345SYatharth Kocharendfunc plat_reset_handler
208*6f249345SYatharth Kochar
209*6f249345SYatharth Kochar	/* -----------------------------------------------------
210*6f249345SYatharth Kochar	 *  unsigned int plat_arm_calc_core_pos(u_register_t mpidr)
211*6f249345SYatharth Kochar	 *  Helper function to calculate the core position.
212*6f249345SYatharth Kochar	 * -----------------------------------------------------
213*6f249345SYatharth Kochar	 */
214*6f249345SYatharth Kocharfunc plat_arm_calc_core_pos
215*6f249345SYatharth Kochar	b	css_calc_core_pos_swap_cluster
216*6f249345SYatharth Kocharendfunc plat_arm_calc_core_pos
217