1 /* 2 * Copyright (c) 2019, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <common/tbbr/tbbr_img_def.h> 11 #include <lib/utils_def.h> 12 #include <lib/xlat_tables/xlat_tables_defs.h> 13 #include <plat/arm/board/common/v2m_def.h> 14 #include <plat/common/common_def.h> 15 16 #include "../fvp_ve_def.h" 17 18 #define ARM_CACHE_WRITEBACK_SHIFT 6 19 20 /* Memory location options for TSP */ 21 #define ARM_DRAM_ID 2 22 23 #define ARM_DRAM1_BASE UL(0x80000000) 24 #define ARM_DRAM1_SIZE UL(0x80000000) 25 #define ARM_DRAM1_END (ARM_DRAM1_BASE + \ 26 ARM_DRAM1_SIZE - 1) 27 28 #define ARM_DRAM2_BASE UL(0x880000000) 29 #define ARM_DRAM2_SIZE PLAT_ARM_DRAM2_SIZE 30 #define ARM_DRAM2_END (ARM_DRAM2_BASE + \ 31 ARM_DRAM2_SIZE - 1) 32 33 #define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE 34 /* 35 * The last 2MB is meant to be NOLOAD and will not be zero 36 * initialized. 37 */ 38 #define ARM_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \ 39 0x00200000) 40 41 42 /* The first 4KB of NS DRAM1 are used as shared memory */ 43 #define FVP_VE_SHARED_RAM_BASE ARM_NS_DRAM1_BASE 44 #define FVP_VE_SHARED_RAM_SIZE UL(0x00001000) /* 4 KB */ 45 46 /* The next 252 kB of NS DRAM is used to load the BL images */ 47 #define ARM_BL_RAM_BASE (FVP_VE_SHARED_RAM_BASE + \ 48 FVP_VE_SHARED_RAM_SIZE) 49 #define ARM_BL_RAM_SIZE (PLAT_ARM_BL_PLUS_SHARED_RAM_SIZE - \ 50 FVP_VE_SHARED_RAM_SIZE) 51 52 53 #define ARM_IRQ_SEC_PHY_TIMER 29 54 55 #define ARM_IRQ_SEC_SGI_0 8 56 #define ARM_IRQ_SEC_SGI_1 9 57 #define ARM_IRQ_SEC_SGI_2 10 58 #define ARM_IRQ_SEC_SGI_3 11 59 #define ARM_IRQ_SEC_SGI_4 12 60 #define ARM_IRQ_SEC_SGI_5 13 61 #define ARM_IRQ_SEC_SGI_6 14 62 #define ARM_IRQ_SEC_SGI_7 15 63 64 /* 65 * Define a list of Group 1 Secure and Group 0 interrupt properties as per GICv3 66 * terminology. On a GICv2 system or mode, the lists will be merged and treated 67 * as Group 0 interrupts. 68 */ 69 #define ARM_G1S_IRQ_PROPS(grp) \ 70 INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 71 GIC_INTR_CFG_LEVEL), \ 72 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 73 GIC_INTR_CFG_EDGE), \ 74 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 75 GIC_INTR_CFG_EDGE), \ 76 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 77 GIC_INTR_CFG_EDGE), \ 78 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 79 GIC_INTR_CFG_EDGE), \ 80 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 81 GIC_INTR_CFG_EDGE), \ 82 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 83 GIC_INTR_CFG_EDGE) 84 85 #define ARM_G0_IRQ_PROPS(grp) \ 86 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 87 GIC_INTR_CFG_EDGE) 88 89 #define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \ 90 FVP_VE_SHARED_RAM_BASE, \ 91 FVP_VE_SHARED_RAM_SIZE, \ 92 MT_DEVICE | MT_RW | MT_SECURE) 93 94 #define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \ 95 ARM_NS_DRAM1_BASE, \ 96 ARM_NS_DRAM1_SIZE, \ 97 MT_MEMORY | MT_RW | MT_NS) 98 99 #define ARM_MAP_DRAM2 MAP_REGION_FLAT( \ 100 ARM_DRAM2_BASE, \ 101 ARM_DRAM2_SIZE, \ 102 MT_MEMORY | MT_RW | MT_NS) 103 104 #define ARM_MAP_BL_RO MAP_REGION_FLAT( \ 105 BL_CODE_BASE, \ 106 BL_CODE_END - BL_CODE_BASE, \ 107 MT_CODE | MT_SECURE), \ 108 MAP_REGION_FLAT( \ 109 BL_RO_DATA_BASE, \ 110 BL_RO_DATA_END \ 111 - BL_RO_DATA_BASE, \ 112 MT_RO_DATA | MT_SECURE) 113 114 #if USE_COHERENT_MEM 115 #define ARM_MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \ 116 BL_COHERENT_RAM_BASE, \ 117 BL_COHERENT_RAM_END \ 118 - BL_COHERENT_RAM_BASE, \ 119 MT_DEVICE | MT_RW | MT_SECURE) 120 #endif 121 122 /* 123 * The max number of regions like RO(code), coherent and data required by 124 * different BL stages which need to be mapped in the MMU. 125 */ 126 #define ARM_BL_REGIONS 5 127 128 #define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \ 129 ARM_BL_REGIONS) 130 131 /* Memory mapped Generic timer interfaces */ 132 #define FVP_VE_TIMER_BASE_FREQUENCY UL(24000000) 133 #define ARM_SYS_CNTREAD_BASE UL(0x2a800000) 134 #define ARM_SYS_CNT_BASE_S UL(0x2a820000) 135 #define ARM_SYS_CNT_BASE_NS UL(0x2a830000) 136 137 #define ARM_CONSOLE_BAUDRATE 115200 138 139 /* Trusted Watchdog constants */ 140 #define ARM_SP805_TWDG_BASE UL(0x1C0F0000) 141 #define ARM_SP805_TWDG_CLK_HZ 32768 142 /* The TBBR document specifies a watchdog timeout of 256 seconds. SP805 143 * asserts reset after two consecutive countdowns (2 x 128 = 256 sec) */ 144 #define ARM_TWDG_TIMEOUT_SEC 128 145 #define ARM_TWDG_LOAD_VAL (ARM_SP805_TWDG_CLK_HZ * \ 146 ARM_TWDG_TIMEOUT_SEC) 147 148 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 149 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 150 151 /* 152 * This macro defines the deepest retention state possible. A higher state 153 * id will represent an invalid or a power down state. 154 */ 155 #define PLAT_MAX_RET_STATE 1 156 157 /* 158 * This macro defines the deepest power down states possible. Any state ID 159 * higher than this is invalid. 160 */ 161 #define PLAT_MAX_OFF_STATE 2 162 163 /* 164 * Some data must be aligned on the biggest cache line size in the platform. 165 * This is known only to the platform as it might have a combination of 166 * integrated and external caches. 167 */ 168 #define CACHE_WRITEBACK_GRANULE (U(1) << ARM_CACHE_WRITEBACK_SHIFT) 169 170 /* 171 * To enable TB_FW_CONFIG to be loaded by BL1, define the corresponding base 172 * and limit. Leave enough space of BL2 meminfo. 173 */ 174 #define ARM_TB_FW_CONFIG_BASE (ARM_BL_RAM_BASE + sizeof(meminfo_t)) 175 #define ARM_TB_FW_CONFIG_LIMIT (ARM_BL_RAM_BASE + PAGE_SIZE) 176 177 /******************************************************************************* 178 * BL1 specific defines. 179 * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of 180 * addresses. 181 ******************************************************************************/ 182 #define BL1_RO_BASE 0x00000000 183 #define BL1_RO_LIMIT PLAT_ARM_TRUSTED_ROM_SIZE 184 /* 185 * Put BL1 RW at the top of the memory allocated for BL images in NS DRAM. 186 */ 187 #define BL1_RW_BASE (ARM_BL_RAM_BASE + \ 188 ARM_BL_RAM_SIZE - \ 189 (PLAT_ARM_MAX_BL1_RW_SIZE)) 190 #define BL1_RW_LIMIT (ARM_BL_RAM_BASE + \ 191 (ARM_BL_RAM_SIZE)) 192 193 194 /******************************************************************************* 195 * BL2 specific defines. 196 ******************************************************************************/ 197 198 /* 199 * Put BL2 just below BL1. 200 */ 201 #define BL2_BASE (BL1_RW_BASE - FVP_VE_MAX_BL2_SIZE) 202 #define BL2_LIMIT BL1_RW_BASE 203 204 205 /* Put BL32 below BL2 in NS DRAM.*/ 206 #define ARM_BL2_MEM_DESC_BASE ARM_TB_FW_CONFIG_LIMIT 207 208 #define BL32_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\ 209 - PLAT_ARM_MAX_BL32_SIZE) 210 #define BL32_PROGBITS_LIMIT BL2_BASE 211 #define BL32_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 212 213 /* Required platform porting definitions */ 214 #define PLATFORM_CORE_COUNT 1 215 #define PLAT_NUM_PWR_DOMAINS ((FVP_VE_CLUSTER_COUNT + \ 216 PLATFORM_CORE_COUNT) + 1) 217 218 #define PLAT_MAX_PWR_LVL 2 219 220 /* 221 * Other platform porting definitions are provided by included headers 222 */ 223 224 /* 225 * Required ARM standard platform porting definitions 226 */ 227 228 #define PLAT_ARM_BL_PLUS_SHARED_RAM_SIZE 0x00040000 /* 256 KB */ 229 230 #define PLAT_ARM_TRUSTED_ROM_BASE 0x00000000 231 #define PLAT_ARM_TRUSTED_ROM_SIZE 0x04000000 /* 64 MB */ 232 233 #define PLAT_ARM_DRAM2_SIZE ULL(0x80000000) 234 235 /* 236 * Load address of BL33 for this platform port 237 */ 238 #define PLAT_ARM_NS_IMAGE_BASE (ARM_DRAM1_BASE + U(0x8000000)) 239 240 /* 241 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the 242 * plat_arm_mmap array defined for each BL stage. 243 */ 244 #if defined(IMAGE_BL32) 245 # define PLAT_ARM_MMAP_ENTRIES 8 246 # define MAX_XLAT_TABLES 6 247 #else 248 # define PLAT_ARM_MMAP_ENTRIES 12 249 # define MAX_XLAT_TABLES 6 250 #endif 251 252 /* 253 * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size 254 * plus a little space for growth. 255 */ 256 #define PLAT_ARM_MAX_BL1_RW_SIZE 0xB000 257 258 /* 259 * FVP_VE_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a 260 * little space for growth. 261 */ 262 #define FVP_VE_MAX_BL2_SIZE 0x11000 263 264 /* 265 * Since BL32 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL32_SIZE is 266 * calculated using the current SP_MIN PROGBITS debug size plus the sizes of 267 * BL2 and BL1-RW 268 */ 269 #define PLAT_ARM_MAX_BL32_SIZE 0x3B000 270 /* 271 272 * Size of cacheable stacks 273 */ 274 #if defined(IMAGE_BL1) 275 # define PLATFORM_STACK_SIZE 0x440 276 #elif defined(IMAGE_BL2) 277 # define PLATFORM_STACK_SIZE 0x400 278 #elif defined(IMAGE_BL32) 279 # define PLATFORM_STACK_SIZE 0x440 280 #endif 281 282 #define MAX_IO_DEVICES 3 283 #define MAX_IO_HANDLES 4 284 285 /* Reserve the last block of flash for PSCI MEM PROTECT flag */ 286 #define PLAT_ARM_FIP_BASE V2M_FLASH1_BASE 287 #define PLAT_ARM_FIP_MAX_SIZE (V2M_FLASH1_SIZE - V2M_FLASH_BLOCK_SIZE) 288 289 #define PLAT_ARM_NVM_BASE V2M_FLASH1_BASE 290 #define PLAT_ARM_NVM_SIZE (V2M_FLASH1_SIZE - V2M_FLASH_BLOCK_SIZE) 291 292 /* 293 * PL011 related constants 294 */ 295 #define PLAT_ARM_BOOT_UART_BASE V2M_IOFPGA_UART0_BASE 296 #define PLAT_ARM_BOOT_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ 297 298 #define PLAT_ARM_RUN_UART_BASE V2M_IOFPGA_UART1_BASE 299 #define PLAT_ARM_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ 300 301 #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE 302 #define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ 303 304 /* System timer related constants */ 305 #define PLAT_ARM_NSTIMER_FRAME_ID 1 306 307 /* Mailbox base address */ 308 #define FVP_VE_TRUSTED_MAILBOX_BASE FVP_VE_SHARED_RAM_BASE 309 310 /* 311 * GIC related constants to cater for GICv2 312 */ 313 #define PLAT_ARM_GICD_BASE VE_GICD_BASE 314 #define PLAT_ARM_GICC_BASE VE_GICC_BASE 315 316 /* 317 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 318 * terminology. On a GICv2 system or mode, the lists will be merged and treated 319 * as Group 0 interrupts. 320 */ 321 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 322 ARM_G1S_IRQ_PROPS(grp), \ 323 INTR_PROP_DESC(FVP_VE_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 324 GIC_INTR_CFG_LEVEL), \ 325 INTR_PROP_DESC(FVP_VE_IRQ_SEC_SYS_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 326 GIC_INTR_CFG_LEVEL) 327 328 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) 329 330 #endif /* PLATFORM_H */ 331