1 /* 2 * Copyright (c) 2019-2020, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <common/tbbr/tbbr_img_def.h> 11 #include <lib/utils_def.h> 12 #include <lib/xlat_tables/xlat_tables_defs.h> 13 #include <plat/arm/board/common/v2m_def.h> 14 #include <plat/arm/common/smccc_def.h> 15 #include <plat/common/common_def.h> 16 17 #include "../fvp_ve_def.h" 18 19 #define ARM_CACHE_WRITEBACK_SHIFT 6 20 21 /* Memory location options for TSP */ 22 #define ARM_DRAM_ID 2 23 24 #define ARM_DRAM1_BASE UL(0x80000000) 25 #define ARM_DRAM1_SIZE UL(0x80000000) 26 #define ARM_DRAM1_END (ARM_DRAM1_BASE + \ 27 ARM_DRAM1_SIZE - 1) 28 29 #define ARM_DRAM2_BASE PLAT_ARM_DRAM2_BASE 30 #define ARM_DRAM2_SIZE PLAT_ARM_DRAM2_SIZE 31 #define ARM_DRAM2_END (ARM_DRAM2_BASE + \ 32 ARM_DRAM2_SIZE - 1) 33 34 #define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE 35 /* 36 * The last 2MB is meant to be NOLOAD and will not be zero 37 * initialized. 38 */ 39 #define ARM_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \ 40 0x00200000) 41 42 43 /* The first 4KB of NS DRAM1 are used as shared memory */ 44 #define FVP_VE_SHARED_RAM_BASE ARM_NS_DRAM1_BASE 45 #define FVP_VE_SHARED_RAM_SIZE UL(0x00001000) /* 4 KB */ 46 47 /* The next 252 kB of NS DRAM is used to load the BL images */ 48 #define ARM_BL_RAM_BASE (FVP_VE_SHARED_RAM_BASE + \ 49 FVP_VE_SHARED_RAM_SIZE) 50 #define ARM_BL_RAM_SIZE (PLAT_ARM_BL_PLUS_SHARED_RAM_SIZE - \ 51 FVP_VE_SHARED_RAM_SIZE) 52 53 54 #define ARM_IRQ_SEC_PHY_TIMER 29 55 56 #define ARM_IRQ_SEC_SGI_0 8 57 #define ARM_IRQ_SEC_SGI_1 9 58 #define ARM_IRQ_SEC_SGI_2 10 59 #define ARM_IRQ_SEC_SGI_3 11 60 #define ARM_IRQ_SEC_SGI_4 12 61 #define ARM_IRQ_SEC_SGI_5 13 62 #define ARM_IRQ_SEC_SGI_6 14 63 #define ARM_IRQ_SEC_SGI_7 15 64 65 /* 66 * Define a list of Group 1 Secure and Group 0 interrupt properties as per GICv3 67 * terminology. On a GICv2 system or mode, the lists will be merged and treated 68 * as Group 0 interrupts. 69 */ 70 #define ARM_G1S_IRQ_PROPS(grp) \ 71 INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 72 GIC_INTR_CFG_LEVEL), \ 73 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 74 GIC_INTR_CFG_EDGE), \ 75 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 76 GIC_INTR_CFG_EDGE), \ 77 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 78 GIC_INTR_CFG_EDGE), \ 79 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 80 GIC_INTR_CFG_EDGE), \ 81 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 82 GIC_INTR_CFG_EDGE), \ 83 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 84 GIC_INTR_CFG_EDGE) 85 86 #define ARM_G0_IRQ_PROPS(grp) \ 87 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 88 GIC_INTR_CFG_EDGE) 89 90 #define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \ 91 FVP_VE_SHARED_RAM_BASE, \ 92 FVP_VE_SHARED_RAM_SIZE, \ 93 MT_DEVICE | MT_RW | MT_SECURE) 94 95 #define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \ 96 ARM_NS_DRAM1_BASE, \ 97 ARM_NS_DRAM1_SIZE, \ 98 MT_MEMORY | MT_RW | MT_NS) 99 100 #define ARM_MAP_DRAM2 MAP_REGION_FLAT( \ 101 ARM_DRAM2_BASE, \ 102 ARM_DRAM2_SIZE, \ 103 MT_MEMORY | MT_RW | MT_NS) 104 105 #define ARM_MAP_BL_RO MAP_REGION_FLAT( \ 106 BL_CODE_BASE, \ 107 BL_CODE_END - BL_CODE_BASE, \ 108 MT_CODE | MT_SECURE), \ 109 MAP_REGION_FLAT( \ 110 BL_RO_DATA_BASE, \ 111 BL_RO_DATA_END \ 112 - BL_RO_DATA_BASE, \ 113 MT_RO_DATA | MT_SECURE) 114 115 #if USE_COHERENT_MEM 116 #define ARM_MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \ 117 BL_COHERENT_RAM_BASE, \ 118 BL_COHERENT_RAM_END \ 119 - BL_COHERENT_RAM_BASE, \ 120 MT_DEVICE | MT_RW | MT_SECURE) 121 #endif 122 123 /* 124 * The max number of regions like RO(code), coherent and data required by 125 * different BL stages which need to be mapped in the MMU. 126 */ 127 #define ARM_BL_REGIONS 5 128 129 #define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \ 130 ARM_BL_REGIONS) 131 132 /* Memory mapped Generic timer interfaces */ 133 #define FVP_VE_TIMER_BASE_FREQUENCY UL(24000000) 134 #define ARM_SYS_CNTREAD_BASE UL(0x2a800000) 135 #define ARM_SYS_CNT_BASE_S UL(0x2a820000) 136 #define ARM_SYS_CNT_BASE_NS UL(0x2a830000) 137 138 #define ARM_CONSOLE_BAUDRATE 115200 139 140 /* Trusted Watchdog constants */ 141 #define ARM_SP805_TWDG_BASE UL(0x1C0F0000) 142 #define ARM_SP805_TWDG_CLK_HZ 32768 143 /* The TBBR document specifies a watchdog timeout of 256 seconds. SP805 144 * asserts reset after two consecutive countdowns (2 x 128 = 256 sec) */ 145 #define ARM_TWDG_TIMEOUT_SEC 128 146 #define ARM_TWDG_LOAD_VAL (ARM_SP805_TWDG_CLK_HZ * \ 147 ARM_TWDG_TIMEOUT_SEC) 148 149 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 150 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 151 152 /* 153 * This macro defines the deepest retention state possible. A higher state 154 * id will represent an invalid or a power down state. 155 */ 156 #define PLAT_MAX_RET_STATE 1 157 158 /* 159 * This macro defines the deepest power down states possible. Any state ID 160 * higher than this is invalid. 161 */ 162 #define PLAT_MAX_OFF_STATE 2 163 164 /* 165 * Some data must be aligned on the biggest cache line size in the platform. 166 * This is known only to the platform as it might have a combination of 167 * integrated and external caches. 168 */ 169 #define CACHE_WRITEBACK_GRANULE (U(1) << ARM_CACHE_WRITEBACK_SHIFT) 170 171 /* 172 * To enable TB_FW_CONFIG to be loaded by BL1, define the corresponding base 173 * and limit. Leave enough space of BL2 meminfo. 174 */ 175 #define ARM_TB_FW_CONFIG_BASE (ARM_BL_RAM_BASE + sizeof(meminfo_t)) 176 #define ARM_TB_FW_CONFIG_LIMIT (ARM_BL_RAM_BASE + PAGE_SIZE) 177 178 /******************************************************************************* 179 * BL1 specific defines. 180 * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of 181 * addresses. 182 ******************************************************************************/ 183 #define BL1_RO_BASE 0x00000000 184 #define BL1_RO_LIMIT PLAT_ARM_TRUSTED_ROM_SIZE 185 /* 186 * Put BL1 RW at the top of the memory allocated for BL images in NS DRAM. 187 */ 188 #define BL1_RW_BASE (ARM_BL_RAM_BASE + \ 189 ARM_BL_RAM_SIZE - \ 190 (PLAT_ARM_MAX_BL1_RW_SIZE)) 191 #define BL1_RW_LIMIT (ARM_BL_RAM_BASE + \ 192 (ARM_BL_RAM_SIZE)) 193 194 195 /******************************************************************************* 196 * BL2 specific defines. 197 ******************************************************************************/ 198 199 /* 200 * Put BL2 just below BL1. 201 */ 202 #define BL2_BASE (BL1_RW_BASE - FVP_VE_MAX_BL2_SIZE) 203 #define BL2_LIMIT BL1_RW_BASE 204 205 206 /* Put BL32 below BL2 in NS DRAM.*/ 207 #define ARM_BL2_MEM_DESC_BASE ARM_TB_FW_CONFIG_LIMIT 208 209 #define BL32_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\ 210 - PLAT_ARM_MAX_BL32_SIZE) 211 #define BL32_PROGBITS_LIMIT BL2_BASE 212 #define BL32_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 213 214 /* Required platform porting definitions */ 215 #define PLATFORM_CORE_COUNT FVP_VE_CLUSTER_COUNT 216 #define PLAT_NUM_PWR_DOMAINS ((FVP_VE_CLUSTER_COUNT + \ 217 PLATFORM_CORE_COUNT) + U(1)) 218 219 #define PLAT_MAX_PWR_LVL 2 220 221 /* 222 * Other platform porting definitions are provided by included headers 223 */ 224 225 /* 226 * Required ARM standard platform porting definitions 227 */ 228 229 #define PLAT_ARM_BL_PLUS_SHARED_RAM_SIZE 0x00040000 /* 256 KB */ 230 231 #define PLAT_ARM_TRUSTED_ROM_BASE 0x00000000 232 #define PLAT_ARM_TRUSTED_ROM_SIZE 0x04000000 /* 64 MB */ 233 234 #define PLAT_ARM_DRAM2_BASE ULL(0x880000000) 235 #define PLAT_ARM_DRAM2_SIZE ULL(0x80000000) 236 237 /* 238 * Load address of BL33 for this platform port 239 */ 240 #define PLAT_ARM_NS_IMAGE_BASE (ARM_DRAM1_BASE + U(0x8000000)) 241 242 /* 243 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the 244 * plat_arm_mmap array defined for each BL stage. 245 */ 246 #if defined(IMAGE_BL32) 247 # define PLAT_ARM_MMAP_ENTRIES 8 248 # define MAX_XLAT_TABLES 6 249 #else 250 # define PLAT_ARM_MMAP_ENTRIES 12 251 # define MAX_XLAT_TABLES 6 252 #endif 253 254 /* 255 * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size 256 * plus a little space for growth. 257 */ 258 #define PLAT_ARM_MAX_BL1_RW_SIZE 0xB000 259 260 /* 261 * FVP_VE_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a 262 * little space for growth. 263 */ 264 #define FVP_VE_MAX_BL2_SIZE 0x11000 265 266 /* 267 * Since BL32 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL32_SIZE is 268 * calculated using the current SP_MIN PROGBITS debug size plus the sizes of 269 * BL2 and BL1-RW 270 */ 271 #define PLAT_ARM_MAX_BL32_SIZE 0x3B000 272 /* 273 274 * Size of cacheable stacks 275 */ 276 #if defined(IMAGE_BL1) 277 # define PLATFORM_STACK_SIZE 0x440 278 #elif defined(IMAGE_BL2) 279 # define PLATFORM_STACK_SIZE 0x400 280 #elif defined(IMAGE_BL32) 281 # define PLATFORM_STACK_SIZE 0x440 282 #endif 283 284 #define MAX_IO_DEVICES 3 285 #define MAX_IO_HANDLES 4 286 287 /* Reserve the last block of flash for PSCI MEM PROTECT flag */ 288 #define PLAT_ARM_FIP_BASE V2M_FLASH1_BASE 289 #define PLAT_ARM_FIP_MAX_SIZE (V2M_FLASH1_SIZE - V2M_FLASH_BLOCK_SIZE) 290 291 #define PLAT_ARM_NVM_BASE V2M_FLASH1_BASE 292 #define PLAT_ARM_NVM_SIZE (V2M_FLASH1_SIZE - V2M_FLASH_BLOCK_SIZE) 293 294 /* 295 * PL011 related constants 296 */ 297 #define PLAT_ARM_BOOT_UART_BASE V2M_IOFPGA_UART0_BASE 298 #define PLAT_ARM_BOOT_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ 299 300 #define PLAT_ARM_RUN_UART_BASE V2M_IOFPGA_UART1_BASE 301 #define PLAT_ARM_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ 302 303 #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE 304 #define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ 305 306 /* System timer related constants */ 307 #define PLAT_ARM_NSTIMER_FRAME_ID 1 308 309 /* Mailbox base address */ 310 #define FVP_VE_TRUSTED_MAILBOX_BASE FVP_VE_SHARED_RAM_BASE 311 312 /* 313 * GIC related constants to cater for GICv2 314 */ 315 #define PLAT_ARM_GICD_BASE VE_GICD_BASE 316 #define PLAT_ARM_GICC_BASE VE_GICC_BASE 317 318 /* 319 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 320 * terminology. On a GICv2 system or mode, the lists will be merged and treated 321 * as Group 0 interrupts. 322 */ 323 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 324 ARM_G1S_IRQ_PROPS(grp), \ 325 INTR_PROP_DESC(FVP_VE_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 326 GIC_INTR_CFG_LEVEL), \ 327 INTR_PROP_DESC(FVP_VE_IRQ_SEC_SYS_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 328 GIC_INTR_CFG_LEVEL) 329 330 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) 331 332 /* 333 * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes 334 */ 335 #ifdef __aarch64__ 336 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) 337 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) 338 #else 339 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 340 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 341 #endif 342 343 #endif /* PLATFORM_H */ 344