16393c787SUsama Arif /* 26393c787SUsama Arif * Copyright (c) 2019, Arm Limited. All rights reserved. 36393c787SUsama Arif * 46393c787SUsama Arif * SPDX-License-Identifier: BSD-3-Clause 56393c787SUsama Arif */ 66393c787SUsama Arif 76393c787SUsama Arif #ifndef FVP_VE_DEF_H 86393c787SUsama Arif #define FVP_VE_DEF_H 96393c787SUsama Arif 106393c787SUsama Arif #include <lib/utils_def.h> 116393c787SUsama Arif 126393c787SUsama Arif /* Default cluster count for FVP VE */ 13*5b33ad17SDeepika Bhavnani #define FVP_VE_CLUSTER_COUNT U(1) 146393c787SUsama Arif 156393c787SUsama Arif /* Default number of CPUs per cluster on FVP VE */ 16*5b33ad17SDeepika Bhavnani #define FVP_VE_MAX_CPUS_PER_CLUSTER U(1) 176393c787SUsama Arif 186393c787SUsama Arif /* Default number of threads per CPU on FVP VE */ 19*5b33ad17SDeepika Bhavnani #define FVP_VE_MAX_PE_PER_CPU U(1) 206393c787SUsama Arif 21*5b33ad17SDeepika Bhavnani #define FVP_VE_CORE_COUNT U(1) 226393c787SUsama Arif 236393c787SUsama Arif #define FVP_VE_PRIMARY_CPU 0x0 246393c787SUsama Arif 256393c787SUsama Arif /******************************************************************************* 266393c787SUsama Arif * FVP memory map related constants 276393c787SUsama Arif ******************************************************************************/ 286393c787SUsama Arif 296393c787SUsama Arif #define FLASH1_BASE 0x0c000000 306393c787SUsama Arif #define FLASH1_SIZE 0x04000000 316393c787SUsama Arif 326393c787SUsama Arif /* Aggregate of all devices in the first GB */ 336393c787SUsama Arif #define DEVICE0_BASE 0x20000000 346393c787SUsama Arif #define DEVICE0_SIZE 0x0c200000 356393c787SUsama Arif 366393c787SUsama Arif #define NSRAM_BASE 0x2e000000 376393c787SUsama Arif #define NSRAM_SIZE 0x10000 386393c787SUsama Arif 396393c787SUsama Arif #define PCIE_EXP_BASE 0x40000000 406393c787SUsama Arif #define TZRNG_BASE 0x7fe60000 416393c787SUsama Arif 426393c787SUsama Arif #define ARCH_MODEL_VE 0x5 436393c787SUsama Arif 446393c787SUsama Arif /* FVP Power controller base address*/ 456393c787SUsama Arif #define PWRC_BASE UL(0x1c100000) 466393c787SUsama Arif 476393c787SUsama Arif /* FVP SP804 timer frequency is 35 MHz*/ 486393c787SUsama Arif #define SP804_TIMER_CLKMULT 1 496393c787SUsama Arif #define SP804_TIMER_CLKDIV 35 506393c787SUsama Arif 516393c787SUsama Arif /* SP810 controller. FVP specific flags */ 526393c787SUsama Arif #define FVP_SP810_CTRL_TIM0_OV (1 << 16) 536393c787SUsama Arif #define FVP_SP810_CTRL_TIM1_OV (1 << 18) 546393c787SUsama Arif #define FVP_SP810_CTRL_TIM2_OV (1 << 20) 556393c787SUsama Arif #define FVP_SP810_CTRL_TIM3_OV (1 << 22) 566393c787SUsama Arif 576393c787SUsama Arif /******************************************************************************* 586393c787SUsama Arif * GIC-400 & interrupt handling related constants 596393c787SUsama Arif ******************************************************************************/ 606393c787SUsama Arif /* VE compatible GIC memory map */ 616393c787SUsama Arif #define VE_GICD_BASE 0x2c001000 628f73663bSUsama Arif #ifdef ARM_CORTEX_A5 638f73663bSUsama Arif #define VE_GICC_BASE 0x2c000100 648f73663bSUsama Arif #else 656393c787SUsama Arif #define VE_GICC_BASE 0x2c002000 668f73663bSUsama Arif #endif 676393c787SUsama Arif #define VE_GICH_BASE 0x2c004000 686393c787SUsama Arif #define VE_GICV_BASE 0x2c006000 696393c787SUsama Arif 706393c787SUsama Arif #define FVP_VE_IRQ_TZ_WDOG 56 716393c787SUsama Arif #define FVP_VE_IRQ_SEC_SYS_TIMER 57 726393c787SUsama Arif 736393c787SUsama Arif #endif /* FVP_VE_DEF_H */ 74