1*6393c787SUsama Arif /*
2*6393c787SUsama Arif * Copyright (c) 2019, Arm Limited. All rights reserved.
3*6393c787SUsama Arif *
4*6393c787SUsama Arif * SPDX-License-Identifier: BSD-3-Clause
5*6393c787SUsama Arif */
6*6393c787SUsama Arif
7*6393c787SUsama Arif #include <assert.h>
8*6393c787SUsama Arif
9*6393c787SUsama Arif #include <common/debug.h>
10*6393c787SUsama Arif #include <lib/mmio.h>
11*6393c787SUsama Arif #include <platform_def.h>
12*6393c787SUsama Arif #include <plat/arm/common/arm_config.h>
13*6393c787SUsama Arif #include <plat/arm/common/plat_arm.h>
14*6393c787SUsama Arif
15*6393c787SUsama Arif #define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \
16*6393c787SUsama Arif DEVICE0_SIZE, \
17*6393c787SUsama Arif MT_DEVICE | MT_RW | MT_SECURE)
18*6393c787SUsama Arif
19*6393c787SUsama Arif #ifdef IMAGE_BL1
20*6393c787SUsama Arif const mmap_region_t plat_arm_mmap[] = {
21*6393c787SUsama Arif ARM_MAP_SHARED_RAM,
22*6393c787SUsama Arif V2M_MAP_FLASH1_RW,
23*6393c787SUsama Arif V2M_MAP_IOFPGA,
24*6393c787SUsama Arif {0}
25*6393c787SUsama Arif };
26*6393c787SUsama Arif #endif
27*6393c787SUsama Arif #ifdef IMAGE_BL2
28*6393c787SUsama Arif const mmap_region_t plat_arm_mmap[] = {
29*6393c787SUsama Arif ARM_MAP_SHARED_RAM,
30*6393c787SUsama Arif V2M_MAP_FLASH1_RW,
31*6393c787SUsama Arif V2M_MAP_IOFPGA,
32*6393c787SUsama Arif ARM_MAP_NS_DRAM1,
33*6393c787SUsama Arif {0}
34*6393c787SUsama Arif };
35*6393c787SUsama Arif #endif
36*6393c787SUsama Arif #ifdef IMAGE_BL32
37*6393c787SUsama Arif const mmap_region_t plat_arm_mmap[] = {
38*6393c787SUsama Arif ARM_MAP_SHARED_RAM,
39*6393c787SUsama Arif V2M_MAP_IOFPGA,
40*6393c787SUsama Arif MAP_DEVICE0,
41*6393c787SUsama Arif {0}
42*6393c787SUsama Arif };
43*6393c787SUsama Arif #endif
44*6393c787SUsama Arif
45*6393c787SUsama Arif ARM_CASSERT_MMAP
46*6393c787SUsama Arif
fvp_ve_config_setup(void)47*6393c787SUsama Arif void __init fvp_ve_config_setup(void)
48*6393c787SUsama Arif {
49*6393c787SUsama Arif unsigned int sys_id, arch;
50*6393c787SUsama Arif
51*6393c787SUsama Arif sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID);
52*6393c787SUsama Arif arch = (sys_id >> V2M_SYS_ID_ARCH_SHIFT) & V2M_SYS_ID_ARCH_MASK;
53*6393c787SUsama Arif
54*6393c787SUsama Arif if (arch != ARCH_MODEL_VE) {
55*6393c787SUsama Arif ERROR("This firmware is for FVP VE models\n");
56*6393c787SUsama Arif panic();
57*6393c787SUsama Arif }
58*6393c787SUsama Arif }
59*6393c787SUsama Arif
plat_get_syscnt_freq2(void)60*6393c787SUsama Arif unsigned int plat_get_syscnt_freq2(void)
61*6393c787SUsama Arif {
62*6393c787SUsama Arif return FVP_VE_TIMER_BASE_FREQUENCY;
63*6393c787SUsama Arif }
64