1*6393c787SUsama Arif/* 2*6393c787SUsama Arif * Copyright (c) 2019, Arm Limited. All rights reserved. 3*6393c787SUsama Arif * 4*6393c787SUsama Arif * SPDX-License-Identifier: BSD-3-Clause 5*6393c787SUsama Arif */ 6*6393c787SUsama Arif 7*6393c787SUsama Arif#include <arch.h> 8*6393c787SUsama Arif#include <asm_macros.S> 9*6393c787SUsama Arif#include <platform_def.h> 10*6393c787SUsama Arif 11*6393c787SUsama Arif .globl plat_secondary_cold_boot_setup 12*6393c787SUsama Arif .globl plat_get_my_entrypoint 13*6393c787SUsama Arif .globl plat_is_my_cpu_primary 14*6393c787SUsama Arif 15*6393c787SUsama Arif /* -------------------------------------------------------------------- 16*6393c787SUsama Arif * void plat_secondary_cold_boot_setup (void); 17*6393c787SUsama Arif * 18*6393c787SUsama Arif * For AArch32, cold-booting secondary CPUs is not yet 19*6393c787SUsama Arif * implemented and they panic. 20*6393c787SUsama Arif * -------------------------------------------------------------------- 21*6393c787SUsama Arif */ 22*6393c787SUsama Ariffunc plat_secondary_cold_boot_setup 23*6393c787SUsama Arifcb_panic: 24*6393c787SUsama Arif b cb_panic 25*6393c787SUsama Arifendfunc plat_secondary_cold_boot_setup 26*6393c787SUsama Arif 27*6393c787SUsama Arif /* --------------------------------------------------------------------- 28*6393c787SUsama Arif * unsigned long plat_get_my_entrypoint (void); 29*6393c787SUsama Arif * 30*6393c787SUsama Arif * Main job of this routine is to distinguish between a cold and warm 31*6393c787SUsama Arif * boot. On FVP, this information can be queried from the power 32*6393c787SUsama Arif * controller. The Power Control SYS Status Register (PSYSR) indicates 33*6393c787SUsama Arif * the wake-up reason for the CPU. 34*6393c787SUsama Arif * 35*6393c787SUsama Arif * For a cold boot, return 0. 36*6393c787SUsama Arif * For a warm boot, read the mailbox and return the address it contains. 37*6393c787SUsama Arif * 38*6393c787SUsama Arif * TODO: PSYSR is a common register and should be 39*6393c787SUsama Arif * accessed using locks. Since it is not possible 40*6393c787SUsama Arif * to use locks immediately after a cold reset 41*6393c787SUsama Arif * we are relying on the fact that after a cold 42*6393c787SUsama Arif * reset all cpus will read the same WK field 43*6393c787SUsama Arif * --------------------------------------------------------------------- 44*6393c787SUsama Arif */ 45*6393c787SUsama Ariffunc plat_get_my_entrypoint 46*6393c787SUsama Arif /* TODO support warm boot */ 47*6393c787SUsama Arif /* Cold reset */ 48*6393c787SUsama Arif mov r0, #0 49*6393c787SUsama Arif bx lr 50*6393c787SUsama Arif 51*6393c787SUsama Arifendfunc plat_get_my_entrypoint 52*6393c787SUsama Arif 53*6393c787SUsama Arif /* ----------------------------------------------------- 54*6393c787SUsama Arif * unsigned int plat_is_my_cpu_primary (void); 55*6393c787SUsama Arif * 56*6393c787SUsama Arif * Currently configured for a sigle CPU 57*6393c787SUsama Arif * ----------------------------------------------------- 58*6393c787SUsama Arif */ 59*6393c787SUsama Ariffunc plat_is_my_cpu_primary 60*6393c787SUsama Arif mov r0, #1 61*6393c787SUsama Arif bx lr 62*6393c787SUsama Arifendfunc plat_is_my_cpu_primary 63