1# 2# Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7include common/fdt_wrappers.mk 8 9# Use the GICv3 driver on the FVP by default 10FVP_USE_GIC_DRIVER := FVP_GICV3 11 12# Default cluster count for FVP 13FVP_CLUSTER_COUNT := 2 14 15# Default number of CPUs per cluster on FVP 16FVP_MAX_CPUS_PER_CLUSTER := 4 17 18# Default number of threads per CPU on FVP 19FVP_MAX_PE_PER_CPU := 1 20 21# Disable redistributor frame of inactive/fused CPU cores by marking it as read 22# only; enable redistributor frames of all CPU cores by default. 23FVP_GICR_REGION_PROTECTION := 0 24 25# Size (in kilobytes) of the Trusted SRAM region to utilize when building for 26# the FVP platform. 27ifeq (${ENABLE_RME},1) 28FVP_TRUSTED_SRAM_SIZE := 384 29else 30FVP_TRUSTED_SRAM_SIZE := 256 31endif 32 33# Macro to enable helpers for running SPM tests. Disabled by default. 34PLAT_TEST_SPM := 0 35 36 37# Enable passing the DT to BL33 in x0 by default. 38USE_KERNEL_DT_CONVENTION := 1 39 40# By default dont build CPUs with no FVP model. 41BUILD_CPUS_WITH_NO_FVP_MODEL ?= 0 42 43ENABLE_FEAT_AMU := 2 44ENABLE_FEAT_AMUv1p1 := 2 45ENABLE_FEAT_HCX := 2 46ENABLE_FEAT_RNG := 2 47ENABLE_FEAT_TWED := 2 48ENABLE_FEAT_GCS := 2 49 50ifeq (${ARCH}, aarch64) 51 52ifeq (${SPM_MM}, 0) 53ifeq (${CTX_INCLUDE_FPREGS}, 0) 54 ENABLE_SME_FOR_NS := 2 55 ENABLE_SME2_FOR_NS := 2 56else 57 ENABLE_SVE_FOR_NS := 0 58 ENABLE_SME_FOR_NS := 0 59 ENABLE_SME2_FOR_NS := 0 60endif 61endif 62 63 ENABLE_BRBE_FOR_NS := 2 64 ENABLE_TRBE_FOR_NS := 2 65 ENABLE_FEAT_D128 := 2 66 ENABLE_FEAT_FPMR := 2 67 ENABLE_FEAT_MOPS := 2 68 ENABLE_FEAT_FGWTE3 := 2 69endif 70 71ENABLE_SYS_REG_TRACE_FOR_NS := 2 72ENABLE_FEAT_CSV2_2 := 2 73ENABLE_FEAT_CSV2_3 := 2 74ENABLE_FEAT_DEBUGV8P9 := 2 75ENABLE_FEAT_DIT := 2 76ENABLE_FEAT_PAN := 2 77ENABLE_FEAT_VHE := 2 78CTX_INCLUDE_NEVE_REGS := 2 79ENABLE_FEAT_SEL2 := 2 80ENABLE_TRF_FOR_NS := 2 81ENABLE_FEAT_ECV := 2 82ENABLE_FEAT_FGT := 2 83ENABLE_FEAT_FGT2 := 2 84ENABLE_FEAT_THE := 2 85ENABLE_FEAT_TCR2 := 2 86ENABLE_FEAT_S2PIE := 2 87ENABLE_FEAT_S1PIE := 2 88ENABLE_FEAT_S2POE := 2 89ENABLE_FEAT_S1POE := 2 90ENABLE_FEAT_SCTLR2 := 2 91ENABLE_FEAT_MTE2 := 2 92ENABLE_FEAT_LS64_ACCDATA := 2 93 94ifeq (${ENABLE_RME},1) 95 ENABLE_FEAT_MEC := 2 96 RMMD_ENABLE_IDE_KEY_PROG := 1 97endif 98 99# The FVP platform depends on this macro to build with correct GIC driver. 100$(eval $(call add_define,FVP_USE_GIC_DRIVER)) 101 102# Pass FVP_CLUSTER_COUNT to the build system. 103$(eval $(call add_define,FVP_CLUSTER_COUNT)) 104 105# Pass FVP_MAX_CPUS_PER_CLUSTER to the build system. 106$(eval $(call add_define,FVP_MAX_CPUS_PER_CLUSTER)) 107 108# Pass FVP_MAX_PE_PER_CPU to the build system. 109$(eval $(call add_define,FVP_MAX_PE_PER_CPU)) 110 111# Pass FVP_GICR_REGION_PROTECTION to the build system. 112$(eval $(call add_define,FVP_GICR_REGION_PROTECTION)) 113 114# Pass FVP_TRUSTED_SRAM_SIZE to the build system. 115$(eval $(call add_define,FVP_TRUSTED_SRAM_SIZE)) 116 117# Sanity check the cluster count and if FVP_CLUSTER_COUNT <= 2, 118# choose the CCI driver , else the CCN driver 119ifeq ($(FVP_CLUSTER_COUNT), 0) 120$(error "Incorrect cluster count specified for FVP port") 121else ifeq ($(FVP_CLUSTER_COUNT),$(filter $(FVP_CLUSTER_COUNT),1 2)) 122FVP_INTERCONNECT_DRIVER := FVP_CCI 123else 124FVP_INTERCONNECT_DRIVER := FVP_CCN 125endif 126 127$(eval $(call add_define,FVP_INTERCONNECT_DRIVER)) 128 129# Choose the GIC sources depending upon the how the FVP will be invoked 130ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV3) 131USE_GIC_DRIVER := 3 132 133# The GIC model (GIC-600 or GIC-500) will be detected at runtime 134GICV3_SUPPORT_GIC600 := 1 135GICV3_OVERRIDE_DISTIF_PWR_OPS := 1 136 137FVP_SECURITY_SOURCES += plat/arm/board/fvp/fvp_gicv3.c 138ifeq ($(filter 1,${RESET_TO_BL2} ${RESET_TO_BL31}),) 139BL31_SOURCES += plat/arm/board/fvp/fconf/fconf_gicv3_config_getter.c 140endif 141 142ifeq (${HW_ASSISTED_COHERENCY}, 0) 143FVP_DT_PREFIX := fvp-base-gicv3-psci 144else 145FVP_DT_PREFIX := fvp-base-gicv3-psci-dynamiq 146endif 147else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV5) 148USE_GIC_DRIVER := 5 149ENABLE_FEAT_GCIE := 1 150BL31_SOURCES += plat/arm/board/fvp/fvp_gicv5.c 151FVP_DT_PREFIX := "FVP does not provide a GICv5 dts yet" 152ifneq ($(SPD),none) 153 $(error Error: GICv5 is not compatible with SPDs) 154endif 155ifeq ($(ENABLE_RME),1) 156 $(error Error: GICv5 is not compatible with RME) 157endif 158else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV2) 159USE_GIC_DRIVER := 2 160 161# No GICv4 extension 162GIC_ENABLE_V4_EXTN := 0 163$(eval $(call add_define,GIC_ENABLE_V4_EXTN)) 164 165FVP_DT_PREFIX := fvp-base-gicv2-psci 166else 167$(error "Incorrect GIC driver chosen on FVP port") 168endif 169 170ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCI) 171FVP_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c 172else ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCN) 173FVP_INTERCONNECT_SOURCES := drivers/arm/ccn/ccn.c \ 174 plat/arm/common/arm_ccn.c 175else 176$(error "Incorrect CCN driver chosen on FVP port") 177endif 178 179FVP_SECURITY_SOURCES += drivers/arm/tzc/tzc400.c \ 180 plat/arm/board/fvp/fvp_security.c \ 181 plat/arm/common/arm_tzc400.c 182 183 184PLAT_INCLUDES := -Iplat/arm/board/fvp/include \ 185 -Iinclude/lib/psa 186 187 188PLAT_BL_COMMON_SOURCES := plat/arm/board/fvp/fvp_common.c 189 190FVP_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S 191 192ifeq (${ARCH}, aarch64) 193 194# select a different set of CPU files, depending on whether we compile for 195# hardware assisted coherency cores or not 196ifeq (${HW_ASSISTED_COHERENCY}, 0) 197# Cores used without DSU 198 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \ 199 lib/cpus/aarch64/cortex_a53.S \ 200 lib/cpus/aarch64/cortex_a57.S \ 201 lib/cpus/aarch64/cortex_a72.S \ 202 lib/cpus/aarch64/cortex_a73.S 203else 204# Cores used with DSU only 205 ifeq (${CTX_INCLUDE_AARCH32_REGS}, 0) 206 # AArch64-only cores 207 # TODO: add all cores to the appropriate lists 208 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a65.S \ 209 lib/cpus/aarch64/cortex_a65ae.S \ 210 lib/cpus/aarch64/cortex_a76.S \ 211 lib/cpus/aarch64/cortex_a76ae.S \ 212 lib/cpus/aarch64/cortex_a77.S \ 213 lib/cpus/aarch64/cortex_a78.S \ 214 lib/cpus/aarch64/cortex_a78_ae.S \ 215 lib/cpus/aarch64/cortex_a78c.S \ 216 lib/cpus/aarch64/cortex_a710.S \ 217 lib/cpus/aarch64/cortex_a715.S \ 218 lib/cpus/aarch64/cortex_a720.S \ 219 lib/cpus/aarch64/cortex_a720_ae.S \ 220 lib/cpus/aarch64/neoverse_n1.S \ 221 lib/cpus/aarch64/neoverse_n2.S \ 222 lib/cpus/aarch64/neoverse_v1.S \ 223 lib/cpus/aarch64/neoverse_e1.S \ 224 lib/cpus/aarch64/cortex_x2.S \ 225 lib/cpus/aarch64/cortex_x4.S 226 endif 227 # AArch64/AArch32 cores 228 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \ 229 lib/cpus/aarch64/cortex_a75.S 230endif 231 232#Include all CPUs to build to support all-errata build. 233ifeq (${ENABLE_ERRATA_ALL},1) 234 BUILD_CPUS_WITH_NO_FVP_MODEL = 1 235 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a320.S \ 236 lib/cpus/aarch64/cortex_a510.S \ 237 lib/cpus/aarch64/cortex_a520.S \ 238 lib/cpus/aarch64/cortex_a725.S \ 239 lib/cpus/aarch64/cortex_x1.S \ 240 lib/cpus/aarch64/cortex_x3.S \ 241 lib/cpus/aarch64/cortex_x925.S \ 242 lib/cpus/aarch64/neoverse_n3.S \ 243 lib/cpus/aarch64/neoverse_v2.S \ 244 lib/cpus/aarch64/neoverse_v3.S 245endif 246 247#Build AArch64-only CPUs with no FVP model yet. 248ifeq (${BUILD_CPUS_WITH_NO_FVP_MODEL},1) 249 # travis/gelas need these 250 ERRATA_SME_POWER_DOWN := 1 251 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_gelas.S \ 252 lib/cpus/aarch64/nevis.S \ 253 lib/cpus/aarch64/travis.S \ 254 lib/cpus/aarch64/cortex_alto.S 255endif 256 257else 258FVP_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S \ 259 lib/cpus/aarch32/cortex_a57.S \ 260 lib/cpus/aarch32/cortex_a53.S 261endif 262 263BL1_SOURCES += drivers/arm/smmu/smmu_v3.c \ 264 drivers/arm/sp805/sp805.c \ 265 drivers/delay_timer/delay_timer.c \ 266 drivers/io/io_semihosting.c \ 267 lib/semihosting/semihosting.c \ 268 lib/semihosting/${ARCH}/semihosting_call.S \ 269 plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 270 plat/arm/board/fvp/fvp_bl1_setup.c \ 271 plat/arm/board/fvp/fvp_cpu_pwr.c \ 272 plat/arm/board/fvp/fvp_err.c \ 273 plat/arm/board/fvp/fvp_io_storage.c \ 274 plat/arm/board/fvp/fvp_topology.c \ 275 ${FVP_CPU_LIBS} \ 276 ${FVP_INTERCONNECT_SOURCES} 277 278ifeq (${USE_SP804_TIMER},1) 279BL1_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 280else 281BL1_SOURCES += drivers/delay_timer/generic_delay_timer.c 282endif 283 284 285BL2_SOURCES += drivers/arm/sp805/sp805.c \ 286 drivers/io/io_semihosting.c \ 287 lib/utils/mem_region.c \ 288 lib/semihosting/semihosting.c \ 289 lib/semihosting/${ARCH}/semihosting_call.S \ 290 plat/arm/board/fvp/fvp_bl2_setup.c \ 291 plat/arm/board/fvp/fvp_err.c \ 292 plat/arm/board/fvp/fvp_io_storage.c \ 293 plat/arm/common/arm_nor_psci_mem_protect.c \ 294 ${FVP_SECURITY_SOURCES} 295 296 297ifeq (${COT_DESC_IN_DTB},1) 298BL2_SOURCES += plat/arm/common/fconf/fconf_nv_cntr_getter.c 299endif 300 301ifeq (${ENABLE_RME},1) 302BL2_SOURCES += plat/arm/board/fvp/aarch64/fvp_helpers.S \ 303 plat/arm/board/fvp/fvp_cpu_pwr.c 304 305BL31_SOURCES += plat/arm/board/fvp/fvp_plat_attest_token.c \ 306 plat/arm/board/fvp/fvp_realm_attest_key.c \ 307 plat/arm/board/fvp/fvp_el3_token_sign.c \ 308 plat/arm/board/fvp/fvp_ide_keymgmt.c 309endif 310 311ifneq (${ENABLE_FEAT_RNG_TRAP},0) 312BL31_SOURCES += plat/arm/board/fvp/fvp_sync_traps.c 313endif 314 315ifeq (${RESET_TO_BL2},1) 316BL2_SOURCES += plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 317 plat/arm/board/fvp/fvp_cpu_pwr.c \ 318 plat/arm/board/fvp/fvp_bl2_el3_setup.c \ 319 ${FVP_CPU_LIBS} \ 320 ${FVP_INTERCONNECT_SOURCES} 321endif 322 323ifeq (${USE_SP804_TIMER},1) 324BL2_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 325endif 326 327BL2U_SOURCES += plat/arm/board/fvp/fvp_bl2u_setup.c \ 328 ${FVP_SECURITY_SOURCES} 329 330ifeq (${USE_SP804_TIMER},1) 331BL2U_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 332endif 333 334BL31_SOURCES += drivers/arm/fvp/fvp_pwrc.c \ 335 drivers/arm/smmu/smmu_v3.c \ 336 drivers/delay_timer/delay_timer.c \ 337 drivers/cfi/v2m/v2m_flash.c \ 338 lib/utils/mem_region.c \ 339 plat/arm/board/fvp/fvp_bl31_setup.c \ 340 plat/arm/board/fvp/fvp_console.c \ 341 plat/arm/board/fvp/fvp_pm.c \ 342 plat/arm/board/fvp/fvp_topology.c \ 343 plat/arm/board/fvp/aarch64/fvp_helpers.S \ 344 plat/arm/board/fvp/fvp_cpu_pwr.c \ 345 plat/arm/common/arm_nor_psci_mem_protect.c \ 346 ${FVP_CPU_LIBS} \ 347 ${FVP_INTERCONNECT_SOURCES} \ 348 ${FVP_SECURITY_SOURCES} 349 350# Support for fconf in BL31 351# Added separately from the above list for better readability 352ifeq ($(filter 1,${RESET_TO_BL2} ${RESET_TO_BL31}),) 353BL31_SOURCES += lib/fconf/fconf.c \ 354 lib/fconf/fconf_dyn_cfg_getter.c \ 355 plat/arm/board/fvp/fconf/fconf_hw_config_getter.c 356 357BL31_SOURCES += ${FDT_WRAPPERS_SOURCES} 358 359ifeq (${SEC_INT_DESC_IN_FCONF},1) 360BL31_SOURCES += plat/arm/common/fconf/fconf_sec_intr_config.c 361endif 362 363endif 364 365ifeq (${USE_SP804_TIMER},1) 366BL31_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 367else 368BL31_SOURCES += drivers/delay_timer/generic_delay_timer.c 369endif 370 371# Add the FDT_SOURCES and options for Dynamic Config (only for Unix env) 372FVP_HW_CONFIG_DTS := fdts/${FVP_DT_PREFIX}.dts 373 374FDT_SOURCES += ${FVP_HW_CONFIG_DTS} 375$(eval FVP_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(FVP_HW_CONFIG_DTS))) 376HW_CONFIG := ${FVP_HW_CONFIG} 377 378# Allow hw_config's secondary-load-address in the DT to be changed 379FVP_HW_CONFIG_ADDR ?= 0x82000000 380DTC_CPPFLAGS += -DFVP_HW_CONFIG_ADDR=$(FVP_HW_CONFIG_ADDR) 381 382# Set default initrd base 128MiB offset of the default kernel address in FVP 383INITRD_BASE ?= 0x90000000 384 385# Kernel base address supports Linux kernels before v5.7 386# DTB base 1MiB before normal base kernel address in FVP (0x88000000) 387ifeq (${ARM_LINUX_KERNEL_AS_BL33},1) 388 PRELOADED_BL33_BASE ?= 0x80080000 389 ifeq (${RESET_TO_BL31},1) 390 ARM_PRELOADED_DTB_BASE ?= 0x87F00000 391 endif 392endif 393 394ifeq (${TRANSFER_LIST}, 0) 395FDT_SOURCES += $(addprefix plat/arm/board/fvp/fdts/, \ 396 ${PLAT}_fw_config.dts \ 397 ${PLAT}_tb_fw_config.dts \ 398 ${PLAT}_soc_fw_config.dts \ 399 ${PLAT}_nt_fw_config.dts \ 400 ) 401 402FVP_TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb 403FVP_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb 404FVP_SOC_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_soc_fw_config.dtb 405FVP_NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb 406 407ifeq (${SPD},tspd) 408FDT_SOURCES += plat/arm/board/fvp/fdts/${PLAT}_tsp_fw_config.dts 409FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tsp_fw_config.dtb 410 411# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 412$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 413endif 414 415# Add the FW_CONFIG to FIP and specify the same to certtool 416$(eval $(call TOOL_ADD_PAYLOAD,${FVP_FW_CONFIG},--fw-config,${FVP_FW_CONFIG})) 417# Add the SOC_FW_CONFIG to FIP and specify the same to certtool 418$(eval $(call TOOL_ADD_PAYLOAD,${FVP_SOC_FW_CONFIG},--soc-fw-config,${FVP_SOC_FW_CONFIG})) 419# Add the NT_FW_CONFIG to FIP and specify the same to certtool 420$(eval $(call TOOL_ADD_PAYLOAD,${FVP_NT_FW_CONFIG},--nt-fw-config,${FVP_NT_FW_CONFIG})) 421# Add the TB_FW_CONFIG to FIP and specify the same to certtool 422$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config,${FVP_TB_FW_CONFIG})) 423endif 424 425ifeq (${SPD},spmd) 426 427ifeq ($(ARM_SPMC_MANIFEST_DTS),) 428ARM_SPMC_MANIFEST_DTS := plat/arm/board/fvp/fdts/${PLAT}_spmc_manifest.dts 429endif 430 431FDT_SOURCES += ${ARM_SPMC_MANIFEST_DTS} 432FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/$(notdir $(basename ${ARM_SPMC_MANIFEST_DTS})).dtb 433 434# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 435$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 436endif 437 438# Add the HW_CONFIG to FIP and specify the same to certtool 439$(eval $(call TOOL_ADD_PAYLOAD,${FVP_HW_CONFIG},--hw-config,${FVP_HW_CONFIG})) 440 441ifeq (${TRANSFER_LIST}, 1) 442 443ifeq ($(RESET_TO_BL31), 1) 444FW_HANDOFF_SIZE := 20000 445 446TRANSFER_LIST_DTB_OFFSET := 0x20 447$(eval $(call add_define,TRANSFER_LIST_DTB_OFFSET)) 448endif 449endif 450 451ifeq (${HOB_LIST}, 1) 452include lib/hob/hob.mk 453endif 454 455# Enable dynamic mitigation support by default 456DYNAMIC_WORKAROUND_CVE_2018_3639 := 1 457 458ifneq (${ENABLE_FEAT_AMU},0) 459BL31_SOURCES += lib/cpus/aarch64/cpuamu.c \ 460 lib/cpus/aarch64/cpuamu_helpers.S 461 462ifeq (${HW_ASSISTED_COHERENCY}, 1) 463BL31_SOURCES += lib/cpus/aarch64/cortex_a75_pubsub.c \ 464 lib/cpus/aarch64/neoverse_n1_pubsub.c 465endif 466endif 467 468ifeq (${HANDLE_EA_EL3_FIRST_NS},1) 469 ifeq (${ENABLE_FEAT_RAS},1) 470 ifeq (${PLATFORM_TEST_FFH_LSP_RAS_SP},1) 471 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_lsp_ras_sp.c 472 else 473 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ras.c 474 endif 475 else 476 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ea.c 477 endif 478endif 479 480ifneq (${ENABLE_STACK_PROTECTOR},0) 481PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_stack_protector.c 482endif 483 484# Enable the dynamic translation tables library. 485ifeq ($(filter 1,${RESET_TO_BL2} ${ARM_XLAT_TABLES_LIB_V1}),) 486 ifeq (${ARCH},aarch32) 487 BL32_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 488 else # AArch64 489 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 490 endif 491endif 492 493ifeq (${ALLOW_RO_XLAT_TABLES}, 1) 494 ifeq (${ARCH},aarch32) 495 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 496 else # AArch64 497 BL31_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 498 ifeq (${SPD},tspd) 499 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 500 endif 501 endif 502endif 503 504ifeq (${USE_DEBUGFS},1) 505 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 506endif 507 508# Add support for platform supplied linker script for BL31 build 509$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT)) 510 511ifneq (${RESET_TO_BL2}, 0) 512 override BL1_SOURCES = 513endif 514 515include plat/arm/board/common/board_common.mk 516include plat/arm/common/arm_common.mk 517 518ifeq (${MEASURED_BOOT},1) 519BL1_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 520 plat/arm/board/fvp/fvp_bl1_measured_boot.c \ 521 lib/psa/measured_boot.c 522 523BL2_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 524 plat/arm/board/fvp/fvp_bl2_measured_boot.c \ 525 lib/psa/measured_boot.c 526endif 527 528ifeq (${DRTM_SUPPORT}, 1) 529BL31_SOURCES += plat/arm/board/fvp/fvp_drtm_addr.c \ 530 plat/arm/board/fvp/fvp_drtm_dma_prot.c \ 531 plat/arm/board/fvp/fvp_drtm_err.c \ 532 plat/arm/board/fvp/fvp_drtm_measurement.c \ 533 plat/arm/board/fvp/fvp_drtm_stub.c \ 534 plat/arm/common/arm_dyn_cfg.c \ 535 plat/arm/board/fvp/fvp_err.c 536endif 537 538ifeq (${TRUSTED_BOARD_BOOT}, 1) 539BL1_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 540BL2_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 541 542# FVP being a development platform, enable capability to disable Authentication 543# dynamically if TRUSTED_BOARD_BOOT is set. 544DYN_DISABLE_AUTH := 1 545endif 546 547ifeq (${SPMC_AT_EL3}, 1) 548PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_el3_spmc.c 549endif 550 551PSCI_OS_INIT_MODE := 1 552 553ifeq (${SPD},spmd) 554BL31_SOURCES += plat/arm/board/fvp/fvp_spmd.c 555endif 556 557# Test specific macros, keep them at bottom of this file 558$(eval $(call add_define,PLATFORM_TEST_EA_FFH)) 559ifeq (${PLATFORM_TEST_EA_FFH}, 1) 560 ifeq (${FFH_SUPPORT}, 0) 561 $(error "PLATFORM_TEST_EA_FFH expects FFH_SUPPORT to be 1") 562 endif 563 564endif 565 566$(eval $(call add_define,PLATFORM_TEST_RAS_FFH)) 567ifeq (${PLATFORM_TEST_RAS_FFH}, 1) 568 ifeq (${ENABLE_FEAT_RAS}, 0) 569 $(error "PLATFORM_TEST_RAS_FFH expects ENABLE_FEAT_RAS to be 1") 570 endif 571 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) 572 $(error "PLATFORM_TEST_RAS_FFH expects HANDLE_EA_EL3_FIRST_NS to be 1") 573 endif 574endif 575 576$(eval $(call add_define,PLATFORM_TEST_FFH_LSP_RAS_SP)) 577ifeq (${PLATFORM_TEST_FFH_LSP_RAS_SP}, 1) 578 ifeq (${PLATFORM_TEST_RAS_FFH}, 1) 579 $(error "PLATFORM_TEST_RAS_FFH is incompatible with PLATFORM_TEST_FFH_LSP_RAS_SP") 580 endif 581 ifeq (${ENABLE_SPMD_LP}, 0) 582 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects ENABLE_SPMD_LP to be 1") 583 endif 584 ifeq (${ENABLE_FEAT_RAS}, 0) 585 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects ENABLE_FEAT_RAS to be 1") 586 endif 587 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) 588 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects HANDLE_EA_EL3_FIRST_NS to be 1") 589 endif 590endif 591 592ifeq (${ERRATA_ABI_SUPPORT}, 1) 593include plat/arm/board/fvp/fvp_cpu_errata.mk 594endif 595 596# Build macro necessary for running SPM tests on FVP platform 597$(eval $(call add_define,PLAT_TEST_SPM)) 598 599ifeq (${LFA_SUPPORT},1) 600BL31_SOURCES += plat/arm/board/fvp/fvp_lfa.c 601endif 602