1 /* 2 * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __PLATFORM_DEF_H__ 32 #define __PLATFORM_DEF_H__ 33 34 #include <arm_def.h> 35 #include <board_arm_def.h> 36 #include <common_def.h> 37 #include <tzc400.h> 38 #include <v2m_def.h> 39 #include "../fvp_def.h" 40 41 /* Required platform porting definitions */ 42 #define PLAT_NUM_PWR_DOMAINS (FVP_CLUSTER_COUNT + \ 43 PLATFORM_CORE_COUNT) 44 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL1 45 #define PLATFORM_CORE_COUNT (FVP_CLUSTER_COUNT * FVP_MAX_CPUS_PER_CLUSTER) 46 47 /* 48 * Other platform porting definitions are provided by included headers 49 */ 50 51 /* 52 * Required ARM standard platform porting definitions 53 */ 54 #define PLAT_ARM_CLUSTER_COUNT FVP_CLUSTER_COUNT 55 56 #define PLAT_ARM_TRUSTED_ROM_BASE 0x00000000 57 #define PLAT_ARM_TRUSTED_ROM_SIZE 0x04000000 /* 64 MB */ 58 59 #define PLAT_ARM_TRUSTED_DRAM_BASE 0x06000000 60 #define PLAT_ARM_TRUSTED_DRAM_SIZE 0x02000000 /* 32 MB */ 61 62 /* No SCP in FVP */ 63 #define PLAT_ARM_SCP_TZC_DRAM1_SIZE ULL(0x0) 64 65 #define PLAT_ARM_DRAM2_SIZE ULL(0x780000000) 66 67 /* 68 * Load address of BL33 for this platform port 69 */ 70 #define PLAT_ARM_NS_IMAGE_OFFSET (ARM_DRAM1_BASE + 0x8000000) 71 72 73 /* 74 * PL011 related constants 75 */ 76 #define PLAT_ARM_BOOT_UART_BASE V2M_IOFPGA_UART0_BASE 77 #define PLAT_ARM_BOOT_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ 78 79 #define PLAT_ARM_BL31_RUN_UART_BASE V2M_IOFPGA_UART1_BASE 80 #define PLAT_ARM_BL31_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ 81 82 #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_BL31_RUN_UART_BASE 83 #define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_BL31_RUN_UART_CLK_IN_HZ 84 85 #define PLAT_ARM_TSP_UART_BASE V2M_IOFPGA_UART2_BASE 86 #define PLAT_ARM_TSP_UART_CLK_IN_HZ V2M_IOFPGA_UART2_CLK_IN_HZ 87 88 /* CCI related constants */ 89 #define PLAT_ARM_CCI_BASE 0x2c090000 90 #define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 3 91 #define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 4 92 93 /* CCN related constants. Only CCN 502 is currently supported */ 94 #define PLAT_ARM_CCN_BASE 0x2e000000 95 #define PLAT_ARM_CLUSTER_TO_CCN_ID_MAP 1, 5, 7, 11 96 97 /* System timer related constants */ 98 #define PLAT_ARM_NSTIMER_FRAME_ID 1 99 100 /* Mailbox base address */ 101 #define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE 102 103 104 /* TrustZone controller related constants 105 * 106 * Currently only filters 0 and 2 are connected on Base FVP. 107 * Filter 0 : CPU clusters (no access to DRAM by default) 108 * Filter 1 : not connected 109 * Filter 2 : LCDs (access to VRAM allowed by default) 110 * Filter 3 : not connected 111 * Programming unconnected filters will have no effect at the 112 * moment. These filter could, however, be connected in future. 113 * So care should be taken not to configure the unused filters. 114 * 115 * Allow only non-secure access to all DRAM to supported devices. 116 * Give access to the CPUs and Virtio. Some devices 117 * would normally use the default ID so allow that too. 118 */ 119 #define PLAT_ARM_TZC_BASE 0x2a4a0000 120 #define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0) 121 122 #define PLAT_ARM_TZC_NS_DEV_ACCESS ( \ 123 TZC_REGION_ACCESS_RDWR(FVP_NSAID_DEFAULT) | \ 124 TZC_REGION_ACCESS_RDWR(FVP_NSAID_PCI) | \ 125 TZC_REGION_ACCESS_RDWR(FVP_NSAID_AP) | \ 126 TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO) | \ 127 TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO_OLD)) 128 129 /* 130 * GIC related constants to cater for both GICv2 and GICv3 instances of an 131 * FVP. They could be overriden at runtime in case the FVP implements the legacy 132 * VE memory map. 133 */ 134 #define PLAT_ARM_GICD_BASE BASE_GICD_BASE 135 #define PLAT_ARM_GICR_BASE BASE_GICR_BASE 136 #define PLAT_ARM_GICC_BASE BASE_GICC_BASE 137 138 /* 139 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 140 * terminology. On a GICv2 system or mode, the lists will be merged and treated 141 * as Group 0 interrupts. 142 */ 143 #define PLAT_ARM_G1S_IRQS ARM_G1S_IRQS, \ 144 FVP_IRQ_TZ_WDOG, \ 145 FVP_IRQ_SEC_SYS_TIMER 146 147 #define PLAT_ARM_G0_IRQS ARM_G0_IRQS 148 149 #endif /* __PLATFORM_DEF_H__ */ 150