1 /* 2 * Copyright (c) 2021-2024, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #ifndef FVP_PAS_DEF_H 7 #define FVP_PAS_DEF_H 8 9 #include <lib/gpt_rme/gpt_rme.h> 10 #include <platform_def.h> 11 12 /***************************************************************************** 13 * PAS regions used to initialize the Granule Protection Table (GPT) 14 ****************************************************************************/ 15 16 /* 17 * The PA space is initially mapped in the GPT as follows: 18 * 19 * ============================================================================ 20 * Base Addr| Size |L? GPT|PAS |Content |Comment 21 * ============================================================================ 22 * 0GB | 1GB |L0 GPT|ANY |TBROM (EL3 code) |Fixed mapping 23 * | | | |TSRAM (EL3 data) | 24 * 00000000 | 40000000 | | |IO (incl.UARTs & GIC) | 25 * ---------------------------------------------------------------------------- 26 * 1GB | 1GB |L0 GPT|ANY |IO |Fixed mapping 27 * 40000000 | 40000000 | | | | 28 * ---------------------------------------------------------------------------- 29 * 2GB | 2GB-64MB |L1 GPT|NS |DRAM (NS Kernel) |Use T.Descrip 30 * 80000000 | 7C000000 | | | | 31 * ---------------------------------------------------------------------------- 32 * 4GB-64MB |64MB-32MB-4MB|L1 GPT|SECURE|DRAM TZC |Use T.Descrip 33 * FC000000 | 1C00000 | | | | 34 * ---------------------------------------------------------------------------- 35 * 4GB-32MB | | | | | 36 * -3MB-1MB | 32MB |L1 GPT|REALM |RMM |Use T.Descrip 37 * FDC00000 | 2000000 | | | | 38 * ---------------------------------------------------------------------------- 39 * 4GB-3MB | | | | | 40 * -1MB | 4MB |L1 GPT|ROOT |EL3 DRAM data, L1 GPTs, |Use T.Descrip 41 * FFC00000 | 400000 | | |SCP TZC | 42 * ---------------------------------------------------------------------------- 43 * 34GB | 2GB |L1 GPT|NS |DRAM (NS Kernel) |Use T.Descrip 44 * 880000000| 80000000 | | | | 45 * ============================================================================ 46 * 47 * - 4KB of L0 GPT reside in TSRAM, on top of the CONFIG section. 48 * - ~1MB of L1 GPTs reside at the top of DRAM1 (TZC area). 49 * - The first 1GB region has GPT_GPI_ANY and, therefore, is not protected by 50 * the GPT. 51 * - The DRAM TZC area is split into three regions: the L1 GPT region and 52 * 3MB of region below that are defined as GPT_GPI_ROOT, 32MB Realm region 53 * below that is defined as GPT_GPI_REALM and the rest of it is defined as 54 * GPT_GPI_SECURE. 55 */ 56 57 /* TODO: This might not be the best way to map the PAS */ 58 59 /* Device memory 0 to 2GB */ 60 #define ARM_PAS_1_BASE (U(0)) 61 #define ARM_PAS_1_SIZE (SZ_2G) /* 2GB */ 62 63 /* NS memory 2GB to (end - 64MB) */ 64 #define ARM_PAS_2_BASE (ARM_PAS_1_BASE + ARM_PAS_1_SIZE) 65 #define ARM_PAS_2_SIZE (ARM_NS_DRAM1_SIZE) 66 67 /* Shared area between EL3 and RMM */ 68 #define ARM_PAS_SHARED_BASE (ARM_EL3_RMM_SHARED_BASE) 69 #define ARM_PAS_SHARED_SIZE (ARM_EL3_RMM_SHARED_SIZE) 70 71 /* Secure TZC region */ 72 #define ARM_PAS_3_BASE (ARM_AP_TZC_DRAM1_BASE) 73 #define ARM_PAS_3_SIZE (ARM_AP_TZC_DRAM1_SIZE) 74 75 /* NS memory 2GB */ 76 #define ARM_PAS_4_BASE ARM_DRAM2_BASE 77 #define ARM_PAS_4_SIZE (SZ_2G) /* 2GB */ 78 79 #define ARM_PAS_GPI_ANY MAP_GPT_REGION(ARM_PAS_1_BASE, \ 80 ARM_PAS_1_SIZE, \ 81 GPT_GPI_ANY) 82 83 #define ARM_PAS_KERNEL GPT_MAP_REGION_GRANULE(ARM_PAS_2_BASE, \ 84 ARM_PAS_2_SIZE, \ 85 GPT_GPI_NS) 86 87 #define ARM_PAS_SECURE GPT_MAP_REGION_GRANULE(ARM_PAS_3_BASE, \ 88 ARM_PAS_3_SIZE, \ 89 GPT_GPI_SECURE) 90 91 #define ARM_PAS_KERNEL_1 GPT_MAP_REGION_GRANULE(ARM_PAS_4_BASE, \ 92 ARM_PAS_4_SIZE, \ 93 GPT_GPI_NS) 94 /* 95 * REALM and Shared area share the same PAS, so consider them a single 96 * PAS region to configure in GPT. 97 */ 98 #define ARM_PAS_REALM GPT_MAP_REGION_GRANULE(ARM_REALM_BASE, \ 99 (ARM_PAS_SHARED_SIZE + \ 100 ARM_REALM_SIZE), \ 101 GPT_GPI_REALM) 102 /* Check if the EL3 TZC DRAM is contiguous with L1 GPT region. */ 103 #if (ARM_L1_GPT_BASE != (ARM_EL3_TZC_DRAM1_BASE + ARM_EL3_TZC_DRAM1_SIZE)) 104 #define ARM_PAS_EL3_DRAM GPT_MAP_REGION_GRANULE(ARM_EL3_TZC_DRAM1_BASE, \ 105 ARM_EL3_TZC_DRAM1_SIZE, \ 106 GPT_GPI_ROOT) 107 108 #define ARM_PAS_GPTS GPT_MAP_REGION_GRANULE(ARM_L1_GPT_BASE, \ 109 ARM_L1_GPT_SIZE, \ 110 GPT_GPI_ROOT) 111 #else 112 /* Contiguous ROOT region */ 113 #define ARM_PAS_EL3_DRAM GPT_MAP_REGION_GRANULE(ARM_EL3_TZC_DRAM1_BASE, \ 114 ARM_EL3_TZC_DRAM1_SIZE + \ 115 ARM_L1_GPT_SIZE, \ 116 GPT_GPI_ROOT) 117 #endif 118 119 /* GPT Configuration options */ 120 #define PLATFORM_L0GPTSZ GPCCR_L0GPTSZ_30BITS 121 122 #endif /* FVP_PAS_DEF_H */ 123