1--- 2name: gicv5_config 3version: 1 4 5GIC_TOP: 6 - pa_range: 6 # 0b0110 52 bits, 4PB (should match the 'System' PA size) 7 8 IWB: 9 - name: "iwb0" 10 config_frame_base_address: 0x2F000000 11 target_itsid: 0 12 num_wires: 64 # 16 bit value 13 device_id: 64 # 16 bit value 14 domains: 7 15 iwb_id: 0 16 17 ITS: 18 - name: "its0" 19 itsid: 0 20 target_irsid: 0 21 # The maximum permitted value of this field is 32 (dec). 22 device_id_bits: 20 23 # The maximum permitted value of this field is 32 (dec). 24 event_id_bits: 0x10 25 # 0b00 - linear DT only. 0b01 linear and 2-level DT supported. 26 device_table_levels: 0x01 27 # 0b00 - linear ITT only. 0b01 linear and 2-level ITT supported. 28 interrupt_translation_table_levels: 0x01 29 has_swerr_reporting: false 30 domains: 31 - type: Non_Secure 32 config_frame_base_address: 0x2F120000 33 translate_frame_base_addresses: [0x2F130000] 34 - type: Secure 35 config_frame_base_address: 0x2F100000 36 translate_frame_base_addresses: [0x2F110000] 37 - type: EL3 38 config_frame_base_address: 0x2F140000 39 translate_frame_base_addresses: [0x2F150000] 40 41 IRS: 42 COMMON: 43 # SPI range supported across all the IRSs. 44 spi_range: 256 45 # Implement set LPI register frame. 46 support_setlpi_frame: true 47 # The minimum number of LPI ID Bits supported. (The maximum value 48 # supported for this field is 14.) 49 min_lpi_id_bits: 0 50 # The maximum number of LPI ID Bits supported. (The maximum value 51 # supported for this field is 24.) 52 max_lpi_id_bits: 24 53 # Levels supported for the IST, possible values [1 - 2], '1' is the 54 # default, '2' means 2-level structure is supported. 55 ist_levels: 2 56 # Reports whether the IRS stores metadata in the level 2 ISTEs, 57 # default is 'false' which means that IST entries don't require storage 58 # for metadata. 59 istmd: false 60 # Supported split values when a 2-level IST structure is used. possible 61 # values are from 1 to 7, '1' is default means Level 2 IST sizes 62 # supported: 4KB 63 ist_splits: 7 64 # Minimum number of LPI ID bits which requires a level 2 ISTE size of 16 65 # bytes to store metadata. 66 istmd_sz: 0 67 INSTANCES: 68 - name: "irs0" 69 irsid: 0 70 # SPI range supported for this IRS instance. 71 spi_irs_range: 256 72 # The minimum SPI ID implemented for this IRS instance. 73 spi_base: 0 74 domains: 75 - config_frame_base_address: 0x2F1A0000 76 lpi_frame_base_address: 0x2F1B0000 77 type: Non_Secure 78 - config_frame_base_address: 0x2F180000 79 lpi_frame_base_address: 0x2F190000 80 type: Secure 81 - config_frame_base_address: 0x2F1C0000 82 lpi_frame_base_address: 0x2F1D0000 83 type: EL3 84 # The affinities of the PEs connected to this IRS instance 85 # [ the order should be matching the platform connections in the LISA 86 # file]. 87 processing_element_affinities: [0, 1, 2, 3, 4, 5, 6, 7] 88 89 90CPU_INTERFACE: 91 # Core ID of the Core implementing the CPUIF (starting from 0) 92 - core_id: 0 93 has_gicv5_legacy: false 94 supported_int_id_bits: 16 95 # Number of non-architected PPIs to be implemented starting from the PPI ID 64. 96 number_of_non_arch_ppis_implemented: 0 97 - core_id: 1 98 has_gicv5_legacy: false 99 supported_int_id_bits: 16 100 number_of_non_arch_ppis_implemented: 0 101 - core_id: 2 102 has_gicv5_legacy: false 103 supported_int_id_bits: 16 104 number_of_non_arch_ppis_implemented: 0 105 - core_id: 3 106 has_gicv5_legacy: false 107 supported_int_id_bits: 16 108 number_of_non_arch_ppis_implemented: 0 109 - core_id: 4 110 has_gicv5_legacy: false 111 supported_int_id_bits: 16 112 number_of_non_arch_ppis_implemented: 0 113 - core_id: 5 114 has_gicv5_legacy: false 115 supported_int_id_bits: 16 116 number_of_non_arch_ppis_implemented: 0 117 - core_id: 6 118 has_gicv5_legacy: false 119 supported_int_id_bits: 16 120 number_of_non_arch_ppis_implemented: 0 121 - core_id: 7 122 has_gicv5_legacy: false 123 supported_int_id_bits: 16 124 number_of_non_arch_ppis_implemented: 0 125