xref: /rk3399_ARM-atf/plat/arm/board/fvp/gicv5_config.yaml (revision e394a717aec18c3f11737a9765f4bd93a2ca7e8c)

---
name: gicv5_config
version: 1

GIC_TOP:
  - pa_range: 6 # 0b0110   52 bits, 4PB (should match the 'System' PA size)

    IWB:
      - name: "iwb0"
        config_frame_base_address: 0x2F000000
        target_itsid: 0
        num_wires: 64        # 16 bit value
        device_id: 64        # 16 bit value
        domains: 7
        iwb_id: 0

    ITS:
      - name: "its0"
        itsid: 0
        target_irsid: 0
        # The maximum permitted value of this field is 32 (dec).
        device_id_bits: 20
        # The maximum permitted value of this field is 32 (dec).
        event_id_bits: 0x10
        # 0b00 - linear DT only. 0b01 linear and 2-level DT supported.
        device_table_levels: 0x01
        # 0b00 - linear ITT only. 0b01 linear and 2-level ITT supported.
        interrupt_translation_table_levels: 0x01
        has_swerr_reporting: false
        domains:
            - type: Non_Secure
              config_frame_base_address: 0x2F120000
              translate_frame_base_addresses: [0x2F130000]
            - type: Secure
              config_frame_base_address: 0x2F100000
              translate_frame_base_addresses: [0x2F110000]
            - type: EL3
              config_frame_base_address: 0x2F140000
              translate_frame_base_addresses: [0x2F150000]

    IRS:
      COMMON:
      # SPI range supported across all the IRSs.
        spi_range: 256
        # Implement set LPI register frame.
        support_setlpi_frame: true
        # The minimum number of LPI ID Bits supported. (The maximum value
        # supported for this field is 14.)
        min_lpi_id_bits: 0
        # The maximum number of LPI ID Bits supported. (The maximum value
        # supported for this field is 24.)
        max_lpi_id_bits: 24
        # Levels supported for the IST, possible values [1 - 2], '1' is the
        # default, '2' means 2-level structure is supported.
        ist_levels: 2
        # Reports whether the IRS stores metadata in the level 2 ISTEs,
        # default is 'false' which means that IST entries don't require storage
        # for metadata.
        istmd: false
        # Supported split values when a 2-level IST structure is used. possible
        # values are from 1 to 7, '1' is default means Level 2 IST sizes
        # supported: 4KB
        ist_splits: 7
        # Minimum number of LPI ID bits which requires a level 2 ISTE size of 16
        # bytes to store metadata.
        istmd_sz: 0
      INSTANCES:
        - name: "irs0"
          irsid: 0
          # SPI range supported for this IRS instance.
          spi_irs_range: 256
          # The minimum SPI ID implemented for this IRS instance.
          spi_base: 0
          domains:
            - config_frame_base_address: 0x2F1A0000
              lpi_frame_base_address: 0x2F1B0000
              type: Non_Secure
            - config_frame_base_address: 0x2F180000
              lpi_frame_base_address: 0x2F190000
              type: Secure
            - config_frame_base_address: 0x2F1C0000
              lpi_frame_base_address: 0x2F1D0000
              type: EL3
          # The affinities of the PEs connected to this IRS instance
          # [ the order should be matching the platform connections in the LISA
          #   file].
          processing_element_affinities: [0, 1, 2, 3, 4, 5, 6, 7]


CPU_INTERFACE:
  # Core ID of the Core implementing the CPUIF (starting from 0)
  - core_id: 0
    has_gicv5_legacy: false
    supported_int_id_bits: 16
    # Number of non-architected PPIs to be implemented starting from the PPI ID 64.
    number_of_non_arch_ppis_implemented: 0
  - core_id: 1
    has_gicv5_legacy: false
    supported_int_id_bits: 16
    number_of_non_arch_ppis_implemented: 0
  - core_id: 2
    has_gicv5_legacy: false
    supported_int_id_bits: 16
    number_of_non_arch_ppis_implemented: 0
  - core_id: 3
    has_gicv5_legacy: false
    supported_int_id_bits: 16
    number_of_non_arch_ppis_implemented: 0
  - core_id: 4
    has_gicv5_legacy: false
    supported_int_id_bits: 16
    number_of_non_arch_ppis_implemented: 0
  - core_id: 5
    has_gicv5_legacy: false
    supported_int_id_bits: 16
    number_of_non_arch_ppis_implemented: 0
  - core_id: 6
    has_gicv5_legacy: false
    supported_int_id_bits: 16
    number_of_non_arch_ppis_implemented: 0
  - core_id: 7
    has_gicv5_legacy: false
    supported_int_id_bits: 16
    number_of_non_arch_ppis_implemented: 0