1 /* 2 * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arm_config.h> 9 #include <cassert.h> 10 #include <plat_arm.h> 11 #include <platform_def.h> 12 #include "drivers/pwrc/fvp_pwrc.h" 13 14 /* The FVP power domain tree descriptor */ 15 unsigned char fvp_power_domain_tree_desc[FVP_CLUSTER_COUNT + 2]; 16 17 18 CASSERT(FVP_CLUSTER_COUNT && FVP_CLUSTER_COUNT <= 256, assert_invalid_fvp_cluster_count); 19 20 /******************************************************************************* 21 * This function dynamically constructs the topology according to 22 * FVP_CLUSTER_COUNT and returns it. 23 ******************************************************************************/ 24 const unsigned char *plat_get_power_domain_tree_desc(void) 25 { 26 unsigned int i; 27 28 /* 29 * The highest level is the system level. The next level is constituted 30 * by clusters and then cores in clusters. 31 */ 32 fvp_power_domain_tree_desc[0] = 1; 33 fvp_power_domain_tree_desc[1] = FVP_CLUSTER_COUNT; 34 35 for (i = 0; i < FVP_CLUSTER_COUNT; i++) 36 fvp_power_domain_tree_desc[i + 2] = FVP_MAX_CPUS_PER_CLUSTER; 37 38 39 return fvp_power_domain_tree_desc; 40 } 41 42 /******************************************************************************* 43 * This function returns the core count within the cluster corresponding to 44 * `mpidr`. 45 ******************************************************************************/ 46 unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr) 47 { 48 return FVP_MAX_CPUS_PER_CLUSTER; 49 } 50 51 /******************************************************************************* 52 * This function implements a part of the critical interface between the psci 53 * generic layer and the platform that allows the former to query the platform 54 * to convert an MPIDR to a unique linear index. An error code (-1) is returned 55 * in case the MPIDR is invalid. 56 ******************************************************************************/ 57 int plat_core_pos_by_mpidr(u_register_t mpidr) 58 { 59 unsigned int clus_id, cpu_id, thread_id; 60 61 /* Validate affinity fields */ 62 if (arm_config.flags & ARM_CONFIG_FVP_SHIFTED_AFF) { 63 thread_id = MPIDR_AFFLVL0_VAL(mpidr); 64 cpu_id = MPIDR_AFFLVL1_VAL(mpidr); 65 clus_id = MPIDR_AFFLVL2_VAL(mpidr); 66 } else { 67 thread_id = 0; 68 cpu_id = MPIDR_AFFLVL0_VAL(mpidr); 69 clus_id = MPIDR_AFFLVL1_VAL(mpidr); 70 } 71 72 if (clus_id >= FVP_CLUSTER_COUNT) 73 return -1; 74 if (cpu_id >= FVP_MAX_CPUS_PER_CLUSTER) 75 return -1; 76 if (thread_id >= FVP_MAX_PE_PER_CPU) 77 return -1; 78 79 if (fvp_pwrc_read_psysr(mpidr) == PSYSR_INVALID) 80 return -1; 81 82 /* 83 * Core position calculation for FVP platform depends on the MT bit in 84 * MPIDR. This function cannot assume that the supplied MPIDR has the MT 85 * bit set even if the implementation has. For example, PSCI clients 86 * might supply MPIDR values without the MT bit set. Therefore, we 87 * inject the current PE's MT bit so as to get the calculation correct. 88 * This of course assumes that none or all CPUs on the platform has MT 89 * bit set. 90 */ 91 mpidr |= (read_mpidr_el1() & MPIDR_MT_MASK); 92 return plat_arm_calc_core_pos(mpidr); 93 } 94