1 /* 2 * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arm_config.h> 9 #include <cassert.h> 10 #include <plat_arm.h> 11 #include <platform.h> 12 #include <platform_def.h> 13 #include "drivers/pwrc/fvp_pwrc.h" 14 15 /* The FVP power domain tree descriptor */ 16 static unsigned char fvp_power_domain_tree_desc[FVP_CLUSTER_COUNT + 2]; 17 18 19 CASSERT(((FVP_CLUSTER_COUNT > 0) && (FVP_CLUSTER_COUNT <= 256)), 20 assert_invalid_fvp_cluster_count); 21 22 /******************************************************************************* 23 * This function dynamically constructs the topology according to 24 * FVP_CLUSTER_COUNT and returns it. 25 ******************************************************************************/ 26 const unsigned char *plat_get_power_domain_tree_desc(void) 27 { 28 int i; 29 30 /* 31 * The highest level is the system level. The next level is constituted 32 * by clusters and then cores in clusters. 33 */ 34 fvp_power_domain_tree_desc[0] = 1; 35 fvp_power_domain_tree_desc[1] = FVP_CLUSTER_COUNT; 36 37 for (i = 0; i < FVP_CLUSTER_COUNT; i++) 38 fvp_power_domain_tree_desc[i + 2] = FVP_MAX_CPUS_PER_CLUSTER; 39 40 41 return fvp_power_domain_tree_desc; 42 } 43 44 /******************************************************************************* 45 * This function returns the core count within the cluster corresponding to 46 * `mpidr`. 47 ******************************************************************************/ 48 unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr) 49 { 50 return FVP_MAX_CPUS_PER_CLUSTER; 51 } 52 53 /******************************************************************************* 54 * This function implements a part of the critical interface between the psci 55 * generic layer and the platform that allows the former to query the platform 56 * to convert an MPIDR to a unique linear index. An error code (-1) is returned 57 * in case the MPIDR is invalid. 58 ******************************************************************************/ 59 int plat_core_pos_by_mpidr(u_register_t mpidr) 60 { 61 unsigned int clus_id, cpu_id, thread_id; 62 63 /* Validate affinity fields */ 64 if ((arm_config.flags & ARM_CONFIG_FVP_SHIFTED_AFF) != 0U) { 65 thread_id = MPIDR_AFFLVL0_VAL(mpidr); 66 cpu_id = MPIDR_AFFLVL1_VAL(mpidr); 67 clus_id = MPIDR_AFFLVL2_VAL(mpidr); 68 } else { 69 thread_id = 0; 70 cpu_id = MPIDR_AFFLVL0_VAL(mpidr); 71 clus_id = MPIDR_AFFLVL1_VAL(mpidr); 72 } 73 74 if (clus_id >= FVP_CLUSTER_COUNT) 75 return -1; 76 if (cpu_id >= FVP_MAX_CPUS_PER_CLUSTER) 77 return -1; 78 if (thread_id >= FVP_MAX_PE_PER_CPU) 79 return -1; 80 81 if (fvp_pwrc_read_psysr(mpidr) == PSYSR_INVALID) 82 return -1; 83 84 /* 85 * Core position calculation for FVP platform depends on the MT bit in 86 * MPIDR. This function cannot assume that the supplied MPIDR has the MT 87 * bit set even if the implementation has. For example, PSCI clients 88 * might supply MPIDR values without the MT bit set. Therefore, we 89 * inject the current PE's MT bit so as to get the calculation correct. 90 * This of course assumes that none or all CPUs on the platform has MT 91 * bit set. 92 */ 93 mpidr |= (read_mpidr_el1() & MPIDR_MT_MASK); 94 return (int) plat_arm_calc_core_pos(mpidr); 95 } 96