1 /* 2 * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 10 #include <arch_helpers.h> 11 #include <common/debug.h> 12 #include <drivers/arm/gicv3.h> 13 #include <drivers/arm/fvp/fvp_pwrc.h> 14 #include <lib/extensions/spe.h> 15 #include <lib/mmio.h> 16 #include <lib/psci/psci.h> 17 #include <plat/arm/common/arm_config.h> 18 #include <plat/arm/common/plat_arm.h> 19 #include <plat/common/platform.h> 20 #include <platform_def.h> 21 22 #include "fvp_private.h" 23 #include "../drivers/arm/gic/v3/gicv3_private.h" 24 25 26 #if ARM_RECOM_STATE_ID_ENC 27 /* 28 * The table storing the valid idle power states. Ensure that the 29 * array entries are populated in ascending order of state-id to 30 * enable us to use binary search during power state validation. 31 * The table must be terminated by a NULL entry. 32 */ 33 const unsigned int arm_pm_idle_states[] = { 34 /* State-id - 0x01 */ 35 arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_RET, 36 ARM_PWR_LVL0, PSTATE_TYPE_STANDBY), 37 /* State-id - 0x02 */ 38 arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_OFF, 39 ARM_PWR_LVL0, PSTATE_TYPE_POWERDOWN), 40 /* State-id - 0x22 */ 41 arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_OFF, ARM_LOCAL_STATE_OFF, 42 ARM_PWR_LVL1, PSTATE_TYPE_POWERDOWN), 43 /* State-id - 0x222 */ 44 arm_make_pwrstate_lvl2(ARM_LOCAL_STATE_OFF, ARM_LOCAL_STATE_OFF, 45 ARM_LOCAL_STATE_OFF, ARM_PWR_LVL2, PSTATE_TYPE_POWERDOWN), 46 0, 47 }; 48 #endif 49 50 /******************************************************************************* 51 * Function which implements the common FVP specific operations to power down a 52 * cluster in response to a CPU_OFF or CPU_SUSPEND request. 53 ******************************************************************************/ 54 static void fvp_cluster_pwrdwn_common(void) 55 { 56 uint64_t mpidr = read_mpidr_el1(); 57 58 #if ENABLE_SPE_FOR_LOWER_ELS 59 /* 60 * On power down we need to disable statistical profiling extensions 61 * before exiting coherency. 62 */ 63 spe_disable(); 64 #endif 65 66 /* Disable coherency if this cluster is to be turned off */ 67 fvp_interconnect_disable(); 68 69 /* Program the power controller to turn the cluster off */ 70 fvp_pwrc_write_pcoffr(mpidr); 71 } 72 73 /* 74 * Empty implementation of these hooks avoid setting the GICR_WAKER.Sleep bit 75 * on ARM GICv3 implementations on FVP. This is required, because FVP does not 76 * support SYSTEM_SUSPEND and it is `faked` in firmware. Hence, for wake up 77 * from `fake` system suspend the GIC must not be powered off. 78 */ 79 void arm_gicv3_distif_pre_save(unsigned int rdist_proc_num) 80 {} 81 82 void arm_gicv3_distif_post_restore(unsigned int rdist_proc_num) 83 {} 84 85 static void fvp_power_domain_on_finish_common(const psci_power_state_t *target_state) 86 { 87 unsigned long mpidr; 88 89 assert(target_state->pwr_domain_state[ARM_PWR_LVL0] == 90 ARM_LOCAL_STATE_OFF); 91 92 /* Get the mpidr for this cpu */ 93 mpidr = read_mpidr_el1(); 94 95 /* Perform the common cluster specific operations */ 96 if (target_state->pwr_domain_state[ARM_PWR_LVL1] == 97 ARM_LOCAL_STATE_OFF) { 98 /* 99 * This CPU might have woken up whilst the cluster was 100 * attempting to power down. In this case the FVP power 101 * controller will have a pending cluster power off request 102 * which needs to be cleared by writing to the PPONR register. 103 * This prevents the power controller from interpreting a 104 * subsequent entry of this cpu into a simple wfi as a power 105 * down request. 106 */ 107 fvp_pwrc_write_pponr(mpidr); 108 109 /* Enable coherency if this cluster was off */ 110 fvp_interconnect_enable(); 111 } 112 /* Perform the common system specific operations */ 113 if (target_state->pwr_domain_state[ARM_PWR_LVL2] == 114 ARM_LOCAL_STATE_OFF) 115 arm_system_pwr_domain_resume(); 116 117 /* 118 * Clear PWKUPR.WEN bit to ensure interrupts do not interfere 119 * with a cpu power down unless the bit is set again 120 */ 121 fvp_pwrc_clr_wen(mpidr); 122 } 123 124 125 /******************************************************************************* 126 * FVP handler called when a CPU is about to enter standby. 127 ******************************************************************************/ 128 static void fvp_cpu_standby(plat_local_state_t cpu_state) 129 { 130 131 assert(cpu_state == ARM_LOCAL_STATE_RET); 132 133 /* 134 * Enter standby state 135 * dsb is good practice before using wfi to enter low power states 136 */ 137 dsb(); 138 wfi(); 139 } 140 141 /******************************************************************************* 142 * FVP handler called when a power domain is about to be turned on. The 143 * mpidr determines the CPU to be turned on. 144 ******************************************************************************/ 145 static int fvp_pwr_domain_on(u_register_t mpidr) 146 { 147 int rc = PSCI_E_SUCCESS; 148 unsigned int psysr; 149 150 /* 151 * Ensure that we do not cancel an inflight power off request for the 152 * target cpu. That would leave it in a zombie wfi. Wait for it to power 153 * off and then program the power controller to turn that CPU on. 154 */ 155 do { 156 psysr = fvp_pwrc_read_psysr(mpidr); 157 } while ((psysr & PSYSR_AFF_L0) != 0U); 158 159 fvp_pwrc_write_pponr(mpidr); 160 return rc; 161 } 162 163 /******************************************************************************* 164 * FVP handler called when a power domain is about to be turned off. The 165 * target_state encodes the power state that each level should transition to. 166 ******************************************************************************/ 167 static void fvp_pwr_domain_off(const psci_power_state_t *target_state) 168 { 169 assert(target_state->pwr_domain_state[ARM_PWR_LVL0] == 170 ARM_LOCAL_STATE_OFF); 171 172 /* 173 * If execution reaches this stage then this power domain will be 174 * suspended. Perform at least the cpu specific actions followed 175 * by the cluster specific operations if applicable. 176 */ 177 178 /* Prevent interrupts from spuriously waking up this cpu */ 179 plat_arm_gic_cpuif_disable(); 180 181 /* Turn redistributor off */ 182 plat_arm_gic_redistif_off(); 183 184 /* Program the power controller to power off this cpu. */ 185 fvp_pwrc_write_ppoffr(read_mpidr_el1()); 186 187 if (target_state->pwr_domain_state[ARM_PWR_LVL1] == 188 ARM_LOCAL_STATE_OFF) 189 fvp_cluster_pwrdwn_common(); 190 191 } 192 193 /******************************************************************************* 194 * FVP handler called when a power domain is about to be suspended. The 195 * target_state encodes the power state that each level should transition to. 196 ******************************************************************************/ 197 static void fvp_pwr_domain_suspend(const psci_power_state_t *target_state) 198 { 199 unsigned long mpidr; 200 201 /* 202 * FVP has retention only at cpu level. Just return 203 * as nothing is to be done for retention. 204 */ 205 if (target_state->pwr_domain_state[ARM_PWR_LVL0] == 206 ARM_LOCAL_STATE_RET) 207 return; 208 209 assert(target_state->pwr_domain_state[ARM_PWR_LVL0] == 210 ARM_LOCAL_STATE_OFF); 211 212 /* Get the mpidr for this cpu */ 213 mpidr = read_mpidr_el1(); 214 215 /* Program the power controller to enable wakeup interrupts. */ 216 fvp_pwrc_set_wen(mpidr); 217 218 /* Prevent interrupts from spuriously waking up this cpu */ 219 plat_arm_gic_cpuif_disable(); 220 221 /* 222 * The Redistributor is not powered off as it can potentially prevent 223 * wake up events reaching the CPUIF and/or might lead to losing 224 * register context. 225 */ 226 227 /* Perform the common cluster specific operations */ 228 if (target_state->pwr_domain_state[ARM_PWR_LVL1] == 229 ARM_LOCAL_STATE_OFF) 230 fvp_cluster_pwrdwn_common(); 231 232 /* Perform the common system specific operations */ 233 if (target_state->pwr_domain_state[ARM_PWR_LVL2] == 234 ARM_LOCAL_STATE_OFF) 235 arm_system_pwr_domain_save(); 236 237 /* Program the power controller to power off this cpu. */ 238 fvp_pwrc_write_ppoffr(read_mpidr_el1()); 239 } 240 241 /******************************************************************************* 242 * FVP handler called when a power domain has just been powered on after 243 * being turned off earlier. The target_state encodes the low power state that 244 * each level has woken up from. 245 ******************************************************************************/ 246 static void fvp_pwr_domain_on_finish(const psci_power_state_t *target_state) 247 { 248 fvp_power_domain_on_finish_common(target_state); 249 250 /* Enable the gic cpu interface */ 251 plat_arm_gic_pcpu_init(); 252 253 /* Program the gic per-cpu distributor or re-distributor interface */ 254 plat_arm_gic_cpuif_enable(); 255 } 256 257 /******************************************************************************* 258 * FVP handler called when a power domain has just been powered on after 259 * having been suspended earlier. The target_state encodes the low power state 260 * that each level has woken up from. 261 * TODO: At the moment we reuse the on finisher and reinitialize the secure 262 * context. Need to implement a separate suspend finisher. 263 ******************************************************************************/ 264 static void fvp_pwr_domain_suspend_finish(const psci_power_state_t *target_state) 265 { 266 /* 267 * Nothing to be done on waking up from retention from CPU level. 268 */ 269 if (target_state->pwr_domain_state[ARM_PWR_LVL0] == 270 ARM_LOCAL_STATE_RET) 271 return; 272 273 fvp_power_domain_on_finish_common(target_state); 274 275 /* Enable the gic cpu interface */ 276 plat_arm_gic_cpuif_enable(); 277 } 278 279 /******************************************************************************* 280 * FVP handlers to shutdown/reboot the system 281 ******************************************************************************/ 282 static void __dead2 fvp_system_off(void) 283 { 284 /* Write the System Configuration Control Register */ 285 mmio_write_32(V2M_SYSREGS_BASE + V2M_SYS_CFGCTRL, 286 V2M_CFGCTRL_START | 287 V2M_CFGCTRL_RW | 288 V2M_CFGCTRL_FUNC(V2M_FUNC_SHUTDOWN)); 289 wfi(); 290 ERROR("FVP System Off: operation not handled.\n"); 291 panic(); 292 } 293 294 static void __dead2 fvp_system_reset(void) 295 { 296 /* Write the System Configuration Control Register */ 297 mmio_write_32(V2M_SYSREGS_BASE + V2M_SYS_CFGCTRL, 298 V2M_CFGCTRL_START | 299 V2M_CFGCTRL_RW | 300 V2M_CFGCTRL_FUNC(V2M_FUNC_REBOOT)); 301 wfi(); 302 ERROR("FVP System Reset: operation not handled.\n"); 303 panic(); 304 } 305 306 static int fvp_node_hw_state(u_register_t target_cpu, 307 unsigned int power_level) 308 { 309 unsigned int psysr; 310 int ret; 311 312 /* 313 * The format of 'power_level' is implementation-defined, but 0 must 314 * mean a CPU. We also allow 1 to denote the cluster 315 */ 316 if ((power_level != ARM_PWR_LVL0) && (power_level != ARM_PWR_LVL1)) 317 return PSCI_E_INVALID_PARAMS; 318 319 /* 320 * Read the status of the given MPDIR from FVP power controller. The 321 * power controller only gives us on/off status, so map that to expected 322 * return values of the PSCI call 323 */ 324 psysr = fvp_pwrc_read_psysr(target_cpu); 325 if (psysr == PSYSR_INVALID) 326 return PSCI_E_INVALID_PARAMS; 327 328 if (power_level == ARM_PWR_LVL0) { 329 ret = ((psysr & PSYSR_AFF_L0) != 0U) ? HW_ON : HW_OFF; 330 } else { 331 /* power_level == ARM_PWR_LVL1 */ 332 ret = ((psysr & PSYSR_AFF_L1) != 0U) ? HW_ON : HW_OFF; 333 } 334 335 return ret; 336 } 337 338 /* 339 * The FVP doesn't truly support power management at SYSTEM power domain. The 340 * SYSTEM_SUSPEND will be down-graded to the cluster level within the platform 341 * layer. The `fake` SYSTEM_SUSPEND allows us to validate some of the driver 342 * save and restore sequences on FVP. 343 */ 344 #if !ARM_BL31_IN_DRAM 345 static void fvp_get_sys_suspend_power_state(psci_power_state_t *req_state) 346 { 347 unsigned int i; 348 349 for (i = ARM_PWR_LVL0; i <= PLAT_MAX_PWR_LVL; i++) 350 req_state->pwr_domain_state[i] = ARM_LOCAL_STATE_OFF; 351 } 352 #endif 353 354 /******************************************************************************* 355 * Handler to filter PSCI requests. 356 ******************************************************************************/ 357 /* 358 * The system power domain suspend is only supported only via 359 * PSCI SYSTEM_SUSPEND API. PSCI CPU_SUSPEND request to system power domain 360 * will be downgraded to the lower level. 361 */ 362 static int fvp_validate_power_state(unsigned int power_state, 363 psci_power_state_t *req_state) 364 { 365 int rc; 366 rc = arm_validate_power_state(power_state, req_state); 367 368 /* 369 * Ensure that the system power domain level is never suspended 370 * via PSCI CPU SUSPEND API. Currently system suspend is only 371 * supported via PSCI SYSTEM SUSPEND API. 372 */ 373 req_state->pwr_domain_state[ARM_PWR_LVL2] = ARM_LOCAL_STATE_RUN; 374 return rc; 375 } 376 377 /* 378 * Custom `translate_power_state_by_mpidr` handler for FVP. Unlike in the 379 * `fvp_validate_power_state`, we do not downgrade the system power 380 * domain level request in `power_state` as it will be used to query the 381 * PSCI_STAT_COUNT/RESIDENCY at the system power domain level. 382 */ 383 static int fvp_translate_power_state_by_mpidr(u_register_t mpidr, 384 unsigned int power_state, 385 psci_power_state_t *output_state) 386 { 387 return arm_validate_power_state(power_state, output_state); 388 } 389 390 /******************************************************************************* 391 * Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard 392 * platform layer will take care of registering the handlers with PSCI. 393 ******************************************************************************/ 394 plat_psci_ops_t plat_arm_psci_pm_ops = { 395 .cpu_standby = fvp_cpu_standby, 396 .pwr_domain_on = fvp_pwr_domain_on, 397 .pwr_domain_off = fvp_pwr_domain_off, 398 .pwr_domain_suspend = fvp_pwr_domain_suspend, 399 .pwr_domain_on_finish = fvp_pwr_domain_on_finish, 400 .pwr_domain_suspend_finish = fvp_pwr_domain_suspend_finish, 401 .system_off = fvp_system_off, 402 .system_reset = fvp_system_reset, 403 .validate_power_state = fvp_validate_power_state, 404 .validate_ns_entrypoint = arm_validate_psci_entrypoint, 405 .translate_power_state_by_mpidr = fvp_translate_power_state_by_mpidr, 406 .get_node_hw_state = fvp_node_hw_state, 407 #if !ARM_BL31_IN_DRAM 408 /* 409 * The TrustZone Controller is set up during the warmboot sequence after 410 * resuming the CPU from a SYSTEM_SUSPEND. If BL31 is located in SRAM 411 * this is not a problem but, if it is in TZC-secured DRAM, it tries to 412 * reconfigure the same memory it is running on, causing an exception. 413 */ 414 .get_sys_suspend_power_state = fvp_get_sys_suspend_power_state, 415 #endif 416 .mem_protect_chk = arm_psci_mem_protect_chk, 417 .read_mem_protect = arm_psci_read_mem_protect, 418 .write_mem_protect = arm_nor_psci_write_mem_protect, 419 }; 420 421 const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops) 422 { 423 return ops; 424 } 425