1 /* 2 * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch_helpers.h> 32 #include <arm_config.h> 33 #include <arm_gic.h> 34 #include <assert.h> 35 #include <debug.h> 36 #include <errno.h> 37 #include <mmio.h> 38 #include <platform.h> 39 #include <plat_arm.h> 40 #include <psci.h> 41 #include <v2m_def.h> 42 #include "drivers/pwrc/fvp_pwrc.h" 43 #include "fvp_def.h" 44 #include "fvp_private.h" 45 46 47 #if ARM_RECOM_STATE_ID_ENC 48 /* 49 * The table storing the valid idle power states. Ensure that the 50 * array entries are populated in ascending order of state-id to 51 * enable us to use binary search during power state validation. 52 * The table must be terminated by a NULL entry. 53 */ 54 const unsigned int arm_pm_idle_states[] = { 55 /* State-id - 0x01 */ 56 arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_RET, 57 ARM_PWR_LVL0, PSTATE_TYPE_STANDBY), 58 /* State-id - 0x02 */ 59 arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_OFF, 60 ARM_PWR_LVL0, PSTATE_TYPE_POWERDOWN), 61 /* State-id - 0x22 */ 62 arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_OFF, ARM_LOCAL_STATE_OFF, 63 ARM_PWR_LVL1, PSTATE_TYPE_POWERDOWN), 64 0, 65 }; 66 #endif 67 68 /******************************************************************************* 69 * Private FVP function to program the mailbox for a cpu before it is released 70 * from reset. 71 ******************************************************************************/ 72 static void fvp_program_mailbox(uintptr_t address) 73 { 74 uintptr_t *mailbox = (void *) MBOX_BASE; 75 *mailbox = address; 76 flush_dcache_range((uintptr_t) mailbox, sizeof(*mailbox)); 77 } 78 79 /******************************************************************************* 80 * Function which implements the common FVP specific operations to power down a 81 * cpu in response to a CPU_OFF or CPU_SUSPEND request. 82 ******************************************************************************/ 83 static void fvp_cpu_pwrdwn_common(void) 84 { 85 /* Prevent interrupts from spuriously waking up this cpu */ 86 arm_gic_cpuif_deactivate(); 87 88 /* Program the power controller to power off this cpu. */ 89 fvp_pwrc_write_ppoffr(read_mpidr_el1()); 90 } 91 92 /******************************************************************************* 93 * Function which implements the common FVP specific operations to power down a 94 * cluster in response to a CPU_OFF or CPU_SUSPEND request. 95 ******************************************************************************/ 96 static void fvp_cluster_pwrdwn_common(void) 97 { 98 uint64_t mpidr = read_mpidr_el1(); 99 100 /* Disable coherency if this cluster is to be turned off */ 101 fvp_cci_disable(); 102 103 /* Program the power controller to turn the cluster off */ 104 fvp_pwrc_write_pcoffr(mpidr); 105 } 106 107 /******************************************************************************* 108 * FVP handler called when a CPU is about to enter standby. 109 ******************************************************************************/ 110 void fvp_cpu_standby(plat_local_state_t cpu_state) 111 { 112 113 assert(cpu_state == ARM_LOCAL_STATE_RET); 114 115 /* 116 * Enter standby state 117 * dsb is good practice before using wfi to enter low power states 118 */ 119 dsb(); 120 wfi(); 121 } 122 123 /******************************************************************************* 124 * FVP handler called when a power domain is about to be turned on. The 125 * mpidr determines the CPU to be turned on. 126 ******************************************************************************/ 127 int fvp_pwr_domain_on(u_register_t mpidr) 128 { 129 int rc = PSCI_E_SUCCESS; 130 unsigned int psysr; 131 132 /* 133 * Ensure that we do not cancel an inflight power off request 134 * for the target cpu. That would leave it in a zombie wfi. 135 * Wait for it to power off, program the jump address for the 136 * target cpu and then program the power controller to turn 137 * that cpu on 138 */ 139 do { 140 psysr = fvp_pwrc_read_psysr(mpidr); 141 } while (psysr & PSYSR_AFF_L0); 142 143 fvp_pwrc_write_pponr(mpidr); 144 return rc; 145 } 146 147 /******************************************************************************* 148 * FVP handler called when a power domain is about to be turned off. The 149 * target_state encodes the power state that each level should transition to. 150 ******************************************************************************/ 151 void fvp_pwr_domain_off(const psci_power_state_t *target_state) 152 { 153 assert(target_state->pwr_domain_state[ARM_PWR_LVL0] == 154 ARM_LOCAL_STATE_OFF); 155 156 /* 157 * If execution reaches this stage then this power domain will be 158 * suspended. Perform at least the cpu specific actions followed 159 * by the cluster specific operations if applicable. 160 */ 161 fvp_cpu_pwrdwn_common(); 162 163 if (target_state->pwr_domain_state[ARM_PWR_LVL1] == 164 ARM_LOCAL_STATE_OFF) 165 fvp_cluster_pwrdwn_common(); 166 167 } 168 169 /******************************************************************************* 170 * FVP handler called when a power domain is about to be suspended. The 171 * target_state encodes the power state that each level should transition to. 172 ******************************************************************************/ 173 void fvp_pwr_domain_suspend(const psci_power_state_t *target_state) 174 { 175 unsigned long mpidr; 176 177 /* 178 * FVP has retention only at cpu level. Just return 179 * as nothing is to be done for retention. 180 */ 181 if (target_state->pwr_domain_state[ARM_PWR_LVL0] == 182 ARM_LOCAL_STATE_RET) 183 return; 184 185 assert(target_state->pwr_domain_state[ARM_PWR_LVL0] == 186 ARM_LOCAL_STATE_OFF); 187 188 /* Get the mpidr for this cpu */ 189 mpidr = read_mpidr_el1(); 190 191 /* Program the power controller to enable wakeup interrupts. */ 192 fvp_pwrc_set_wen(mpidr); 193 194 /* Perform the common cpu specific operations */ 195 fvp_cpu_pwrdwn_common(); 196 197 /* Perform the common cluster specific operations */ 198 if (target_state->pwr_domain_state[ARM_PWR_LVL1] == 199 ARM_LOCAL_STATE_OFF) 200 fvp_cluster_pwrdwn_common(); 201 } 202 203 /******************************************************************************* 204 * FVP handler called when a power domain has just been powered on after 205 * being turned off earlier. The target_state encodes the low power state that 206 * each level has woken up from. 207 ******************************************************************************/ 208 void fvp_pwr_domain_on_finish(const psci_power_state_t *target_state) 209 { 210 unsigned long mpidr; 211 212 assert(target_state->pwr_domain_state[ARM_PWR_LVL0] == 213 ARM_LOCAL_STATE_OFF); 214 215 /* Get the mpidr for this cpu */ 216 mpidr = read_mpidr_el1(); 217 218 /* Perform the common cluster specific operations */ 219 if (target_state->pwr_domain_state[ARM_PWR_LVL1] == 220 ARM_LOCAL_STATE_OFF) { 221 /* 222 * This CPU might have woken up whilst the cluster was 223 * attempting to power down. In this case the FVP power 224 * controller will have a pending cluster power off request 225 * which needs to be cleared by writing to the PPONR register. 226 * This prevents the power controller from interpreting a 227 * subsequent entry of this cpu into a simple wfi as a power 228 * down request. 229 */ 230 fvp_pwrc_write_pponr(mpidr); 231 232 /* Enable coherency if this cluster was off */ 233 fvp_cci_enable(); 234 } 235 236 /* 237 * Clear PWKUPR.WEN bit to ensure interrupts do not interfere 238 * with a cpu power down unless the bit is set again 239 */ 240 fvp_pwrc_clr_wen(mpidr); 241 242 /* Enable the gic cpu interface */ 243 arm_gic_cpuif_setup(); 244 245 /* TODO: This setup is needed only after a cold boot */ 246 arm_gic_pcpu_distif_setup(); 247 } 248 249 /******************************************************************************* 250 * FVP handler called when a power domain has just been powered on after 251 * having been suspended earlier. The target_state encodes the low power state 252 * that each level has woken up from. 253 * TODO: At the moment we reuse the on finisher and reinitialize the secure 254 * context. Need to implement a separate suspend finisher. 255 ******************************************************************************/ 256 void fvp_pwr_domain_suspend_finish(const psci_power_state_t *target_state) 257 { 258 /* 259 * Nothing to be done on waking up from retention from CPU level. 260 */ 261 if (target_state->pwr_domain_state[ARM_PWR_LVL0] == 262 ARM_LOCAL_STATE_RET) 263 return; 264 265 fvp_pwr_domain_on_finish(target_state); 266 } 267 268 /******************************************************************************* 269 * FVP handlers to shutdown/reboot the system 270 ******************************************************************************/ 271 static void __dead2 fvp_system_off(void) 272 { 273 /* Write the System Configuration Control Register */ 274 mmio_write_32(V2M_SYSREGS_BASE + V2M_SYS_CFGCTRL, 275 V2M_CFGCTRL_START | 276 V2M_CFGCTRL_RW | 277 V2M_CFGCTRL_FUNC(V2M_FUNC_SHUTDOWN)); 278 wfi(); 279 ERROR("FVP System Off: operation not handled.\n"); 280 panic(); 281 } 282 283 static void __dead2 fvp_system_reset(void) 284 { 285 /* Write the System Configuration Control Register */ 286 mmio_write_32(V2M_SYSREGS_BASE + V2M_SYS_CFGCTRL, 287 V2M_CFGCTRL_START | 288 V2M_CFGCTRL_RW | 289 V2M_CFGCTRL_FUNC(V2M_FUNC_REBOOT)); 290 wfi(); 291 ERROR("FVP System Reset: operation not handled.\n"); 292 panic(); 293 } 294 295 /******************************************************************************* 296 * Export the platform handlers to enable psci to invoke them 297 ******************************************************************************/ 298 static const plat_psci_ops_t fvp_plat_psci_ops = { 299 .cpu_standby = fvp_cpu_standby, 300 .pwr_domain_on = fvp_pwr_domain_on, 301 .pwr_domain_off = fvp_pwr_domain_off, 302 .pwr_domain_suspend = fvp_pwr_domain_suspend, 303 .pwr_domain_on_finish = fvp_pwr_domain_on_finish, 304 .pwr_domain_suspend_finish = fvp_pwr_domain_suspend_finish, 305 .system_off = fvp_system_off, 306 .system_reset = fvp_system_reset, 307 .validate_power_state = arm_validate_power_state, 308 .validate_ns_entrypoint = arm_validate_ns_entrypoint 309 }; 310 311 /******************************************************************************* 312 * Export the platform specific psci ops & initialize the fvp power controller 313 ******************************************************************************/ 314 int plat_setup_psci_ops(uintptr_t sec_entrypoint, 315 const plat_psci_ops_t **psci_ops) 316 { 317 *psci_ops = &fvp_plat_psci_ops; 318 319 /* Program the jump address */ 320 fvp_program_mailbox(sec_entrypoint); 321 return 0; 322 } 323