1 /* 2 * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <arch_helpers.h> 10 #include <common/debug.h> 11 #include <drivers/arm/gicv3.h> 12 #include <drivers/arm/fvp/fvp_pwrc.h> 13 #include <lib/extensions/spe.h> 14 #include <lib/mmio.h> 15 #include <lib/psci/psci.h> 16 #include <plat/arm/common/arm_config.h> 17 #include <plat/arm/common/plat_arm.h> 18 #include <platform_def.h> 19 20 #include "fvp_private.h" 21 #include "../drivers/arm/gic/v3/gicv3_private.h" 22 23 24 #if ARM_RECOM_STATE_ID_ENC 25 /* 26 * The table storing the valid idle power states. Ensure that the 27 * array entries are populated in ascending order of state-id to 28 * enable us to use binary search during power state validation. 29 * The table must be terminated by a NULL entry. 30 */ 31 const unsigned int arm_pm_idle_states[] = { 32 /* State-id - 0x01 */ 33 arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_RET, 34 ARM_PWR_LVL0, PSTATE_TYPE_STANDBY), 35 /* State-id - 0x02 */ 36 arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_OFF, 37 ARM_PWR_LVL0, PSTATE_TYPE_POWERDOWN), 38 /* State-id - 0x22 */ 39 arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_OFF, ARM_LOCAL_STATE_OFF, 40 ARM_PWR_LVL1, PSTATE_TYPE_POWERDOWN), 41 /* State-id - 0x222 */ 42 arm_make_pwrstate_lvl2(ARM_LOCAL_STATE_OFF, ARM_LOCAL_STATE_OFF, 43 ARM_LOCAL_STATE_OFF, ARM_PWR_LVL2, PSTATE_TYPE_POWERDOWN), 44 0, 45 }; 46 #endif 47 48 /******************************************************************************* 49 * Function which implements the common FVP specific operations to power down a 50 * cluster in response to a CPU_OFF or CPU_SUSPEND request. 51 ******************************************************************************/ 52 static void fvp_cluster_pwrdwn_common(void) 53 { 54 uint64_t mpidr = read_mpidr_el1(); 55 56 #if ENABLE_SPE_FOR_LOWER_ELS 57 /* 58 * On power down we need to disable statistical profiling extensions 59 * before exiting coherency. 60 */ 61 spe_disable(); 62 #endif 63 64 /* Disable coherency if this cluster is to be turned off */ 65 fvp_interconnect_disable(); 66 67 #if HW_ASSISTED_COHERENCY 68 uint32_t reg; 69 70 /* 71 * If we have determined this core to be the last man standing and we 72 * intend to power down the cluster proactively, we provide a hint to 73 * the power controller that cluster power is not required when all 74 * cores are powered down. 75 * Note that this is only an advisory to power controller and is supported 76 * by SoCs with DynamIQ Shared Units only. 77 */ 78 reg = read_clusterpwrdn(); 79 80 /* Clear and set bit 0 : Cluster power not required */ 81 reg &= ~DSU_CLUSTER_PWR_MASK; 82 reg |= DSU_CLUSTER_PWR_OFF; 83 write_clusterpwrdn(reg); 84 #endif 85 86 /* Program the power controller to turn the cluster off */ 87 fvp_pwrc_write_pcoffr(mpidr); 88 } 89 90 /* 91 * Empty implementation of these hooks avoid setting the GICR_WAKER.Sleep bit 92 * on ARM GICv3 implementations on FVP. This is required, because FVP does not 93 * support SYSTEM_SUSPEND and it is `faked` in firmware. Hence, for wake up 94 * from `fake` system suspend the GIC must not be powered off. 95 */ 96 void arm_gicv3_distif_pre_save(unsigned int rdist_proc_num) 97 {} 98 99 void arm_gicv3_distif_post_restore(unsigned int rdist_proc_num) 100 {} 101 102 static void fvp_power_domain_on_finish_common(const psci_power_state_t *target_state) 103 { 104 unsigned long mpidr; 105 106 assert(target_state->pwr_domain_state[ARM_PWR_LVL0] == 107 ARM_LOCAL_STATE_OFF); 108 109 /* Get the mpidr for this cpu */ 110 mpidr = read_mpidr_el1(); 111 112 /* Perform the common cluster specific operations */ 113 if (target_state->pwr_domain_state[ARM_PWR_LVL1] == 114 ARM_LOCAL_STATE_OFF) { 115 /* 116 * This CPU might have woken up whilst the cluster was 117 * attempting to power down. In this case the FVP power 118 * controller will have a pending cluster power off request 119 * which needs to be cleared by writing to the PPONR register. 120 * This prevents the power controller from interpreting a 121 * subsequent entry of this cpu into a simple wfi as a power 122 * down request. 123 */ 124 fvp_pwrc_write_pponr(mpidr); 125 126 /* Enable coherency if this cluster was off */ 127 fvp_interconnect_enable(); 128 } 129 /* Perform the common system specific operations */ 130 if (target_state->pwr_domain_state[ARM_PWR_LVL2] == 131 ARM_LOCAL_STATE_OFF) 132 arm_system_pwr_domain_resume(); 133 134 /* 135 * Clear PWKUPR.WEN bit to ensure interrupts do not interfere 136 * with a cpu power down unless the bit is set again 137 */ 138 fvp_pwrc_clr_wen(mpidr); 139 } 140 141 /******************************************************************************* 142 * FVP handler called when a CPU is about to enter standby. 143 ******************************************************************************/ 144 static void fvp_cpu_standby(plat_local_state_t cpu_state) 145 { 146 u_register_t scr = read_scr_el3(); 147 148 assert(cpu_state == ARM_LOCAL_STATE_RET); 149 150 /* 151 * Enable the Non-secure interrupt to wake the CPU. 152 * In GICv3 affinity routing mode, the Non-secure Group 1 interrupts 153 * use Physical FIQ at EL3 whereas in GICv2, Physical IRQ is used. 154 * Enabling both the bits works for both GICv2 mode and GICv3 affinity 155 * routing mode. 156 */ 157 write_scr_el3(scr | SCR_IRQ_BIT | SCR_FIQ_BIT); 158 isb(); 159 160 /* 161 * Enter standby state. 162 * dsb is good practice before using wfi to enter low power states. 163 */ 164 dsb(); 165 wfi(); 166 167 /* 168 * Restore SCR_EL3 to the original value, synchronisation of SCR_EL3 169 * is done by eret in el3_exit() to save some execution cycles. 170 */ 171 write_scr_el3(scr); 172 } 173 174 /******************************************************************************* 175 * FVP handler called when a power domain is about to be turned on. The 176 * mpidr determines the CPU to be turned on. 177 ******************************************************************************/ 178 static int fvp_pwr_domain_on(u_register_t mpidr) 179 { 180 int rc = PSCI_E_SUCCESS; 181 unsigned int psysr; 182 183 /* 184 * Ensure that we do not cancel an inflight power off request for the 185 * target cpu. That would leave it in a zombie wfi. Wait for it to power 186 * off and then program the power controller to turn that CPU on. 187 */ 188 do { 189 psysr = fvp_pwrc_read_psysr(mpidr); 190 } while ((psysr & PSYSR_AFF_L0) != 0U); 191 192 fvp_pwrc_write_pponr(mpidr); 193 return rc; 194 } 195 196 /******************************************************************************* 197 * FVP handler called when a power domain is about to be turned off. The 198 * target_state encodes the power state that each level should transition to. 199 ******************************************************************************/ 200 static void fvp_pwr_domain_off(const psci_power_state_t *target_state) 201 { 202 assert(target_state->pwr_domain_state[ARM_PWR_LVL0] == 203 ARM_LOCAL_STATE_OFF); 204 205 /* 206 * If execution reaches this stage then this power domain will be 207 * suspended. Perform at least the cpu specific actions followed 208 * by the cluster specific operations if applicable. 209 */ 210 211 /* Prevent interrupts from spuriously waking up this cpu */ 212 plat_arm_gic_cpuif_disable(); 213 214 /* Turn redistributor off */ 215 plat_arm_gic_redistif_off(); 216 217 /* Program the power controller to power off this cpu. */ 218 fvp_pwrc_write_ppoffr(read_mpidr_el1()); 219 220 if (target_state->pwr_domain_state[ARM_PWR_LVL1] == 221 ARM_LOCAL_STATE_OFF) 222 fvp_cluster_pwrdwn_common(); 223 224 } 225 226 /******************************************************************************* 227 * FVP handler called when a power domain is about to be suspended. The 228 * target_state encodes the power state that each level should transition to. 229 ******************************************************************************/ 230 static void fvp_pwr_domain_suspend(const psci_power_state_t *target_state) 231 { 232 unsigned long mpidr; 233 234 /* 235 * FVP has retention only at cpu level. Just return 236 * as nothing is to be done for retention. 237 */ 238 if (target_state->pwr_domain_state[ARM_PWR_LVL0] == 239 ARM_LOCAL_STATE_RET) 240 return; 241 242 assert(target_state->pwr_domain_state[ARM_PWR_LVL0] == 243 ARM_LOCAL_STATE_OFF); 244 245 /* Get the mpidr for this cpu */ 246 mpidr = read_mpidr_el1(); 247 248 /* Program the power controller to enable wakeup interrupts. */ 249 fvp_pwrc_set_wen(mpidr); 250 251 /* Prevent interrupts from spuriously waking up this cpu */ 252 plat_arm_gic_cpuif_disable(); 253 254 /* 255 * The Redistributor is not powered off as it can potentially prevent 256 * wake up events reaching the CPUIF and/or might lead to losing 257 * register context. 258 */ 259 260 /* Perform the common cluster specific operations */ 261 if (target_state->pwr_domain_state[ARM_PWR_LVL1] == 262 ARM_LOCAL_STATE_OFF) 263 fvp_cluster_pwrdwn_common(); 264 265 /* Perform the common system specific operations */ 266 if (target_state->pwr_domain_state[ARM_PWR_LVL2] == 267 ARM_LOCAL_STATE_OFF) 268 arm_system_pwr_domain_save(); 269 270 /* Program the power controller to power off this cpu. */ 271 fvp_pwrc_write_ppoffr(read_mpidr_el1()); 272 } 273 274 /******************************************************************************* 275 * FVP handler called when a power domain has just been powered on after 276 * being turned off earlier. The target_state encodes the low power state that 277 * each level has woken up from. 278 ******************************************************************************/ 279 static void fvp_pwr_domain_on_finish(const psci_power_state_t *target_state) 280 { 281 fvp_power_domain_on_finish_common(target_state); 282 283 } 284 285 /******************************************************************************* 286 * FVP handler called when a power domain has just been powered on and the cpu 287 * and its cluster are fully participating in coherent transaction on the 288 * interconnect. Data cache must be enabled for CPU at this point. 289 ******************************************************************************/ 290 static void fvp_pwr_domain_on_finish_late(const psci_power_state_t *target_state) 291 { 292 /* Program GIC per-cpu distributor or re-distributor interface */ 293 plat_arm_gic_pcpu_init(); 294 295 /* Enable GIC CPU interface */ 296 plat_arm_gic_cpuif_enable(); 297 } 298 299 /******************************************************************************* 300 * FVP handler called when a power domain has just been powered on after 301 * having been suspended earlier. The target_state encodes the low power state 302 * that each level has woken up from. 303 * TODO: At the moment we reuse the on finisher and reinitialize the secure 304 * context. Need to implement a separate suspend finisher. 305 ******************************************************************************/ 306 static void fvp_pwr_domain_suspend_finish(const psci_power_state_t *target_state) 307 { 308 /* 309 * Nothing to be done on waking up from retention from CPU level. 310 */ 311 if (target_state->pwr_domain_state[ARM_PWR_LVL0] == 312 ARM_LOCAL_STATE_RET) 313 return; 314 315 fvp_power_domain_on_finish_common(target_state); 316 317 /* Enable GIC CPU interface */ 318 plat_arm_gic_cpuif_enable(); 319 } 320 321 /******************************************************************************* 322 * FVP handlers to shutdown/reboot the system 323 ******************************************************************************/ 324 static void __dead2 fvp_system_off(void) 325 { 326 /* Write the System Configuration Control Register */ 327 mmio_write_32(V2M_SYSREGS_BASE + V2M_SYS_CFGCTRL, 328 V2M_CFGCTRL_START | 329 V2M_CFGCTRL_RW | 330 V2M_CFGCTRL_FUNC(V2M_FUNC_SHUTDOWN)); 331 wfi(); 332 ERROR("FVP System Off: operation not handled.\n"); 333 panic(); 334 } 335 336 static void __dead2 fvp_system_reset(void) 337 { 338 /* Write the System Configuration Control Register */ 339 mmio_write_32(V2M_SYSREGS_BASE + V2M_SYS_CFGCTRL, 340 V2M_CFGCTRL_START | 341 V2M_CFGCTRL_RW | 342 V2M_CFGCTRL_FUNC(V2M_FUNC_REBOOT)); 343 wfi(); 344 ERROR("FVP System Reset: operation not handled.\n"); 345 panic(); 346 } 347 348 static int fvp_node_hw_state(u_register_t target_cpu, 349 unsigned int power_level) 350 { 351 unsigned int psysr; 352 int ret; 353 354 /* 355 * The format of 'power_level' is implementation-defined, but 0 must 356 * mean a CPU. We also allow 1 to denote the cluster 357 */ 358 if ((power_level != ARM_PWR_LVL0) && (power_level != ARM_PWR_LVL1)) 359 return PSCI_E_INVALID_PARAMS; 360 361 /* 362 * Read the status of the given MPDIR from FVP power controller. The 363 * power controller only gives us on/off status, so map that to expected 364 * return values of the PSCI call 365 */ 366 psysr = fvp_pwrc_read_psysr(target_cpu); 367 if (psysr == PSYSR_INVALID) 368 return PSCI_E_INVALID_PARAMS; 369 370 if (power_level == ARM_PWR_LVL0) { 371 ret = ((psysr & PSYSR_AFF_L0) != 0U) ? HW_ON : HW_OFF; 372 } else { 373 /* power_level == ARM_PWR_LVL1 */ 374 ret = ((psysr & PSYSR_AFF_L1) != 0U) ? HW_ON : HW_OFF; 375 } 376 377 return ret; 378 } 379 380 /* 381 * The FVP doesn't truly support power management at SYSTEM power domain. The 382 * SYSTEM_SUSPEND will be down-graded to the cluster level within the platform 383 * layer. The `fake` SYSTEM_SUSPEND allows us to validate some of the driver 384 * save and restore sequences on FVP. 385 */ 386 #if !ARM_BL31_IN_DRAM 387 static void fvp_get_sys_suspend_power_state(psci_power_state_t *req_state) 388 { 389 unsigned int i; 390 391 for (i = ARM_PWR_LVL0; i <= PLAT_MAX_PWR_LVL; i++) 392 req_state->pwr_domain_state[i] = ARM_LOCAL_STATE_OFF; 393 } 394 #endif 395 396 /******************************************************************************* 397 * Handler to filter PSCI requests. 398 ******************************************************************************/ 399 /* 400 * The system power domain suspend is only supported only via 401 * PSCI SYSTEM_SUSPEND API. PSCI CPU_SUSPEND request to system power domain 402 * will be downgraded to the lower level. 403 */ 404 static int fvp_validate_power_state(unsigned int power_state, 405 psci_power_state_t *req_state) 406 { 407 int rc; 408 rc = arm_validate_power_state(power_state, req_state); 409 410 /* 411 * Ensure that the system power domain level is never suspended 412 * via PSCI CPU SUSPEND API. Currently system suspend is only 413 * supported via PSCI SYSTEM SUSPEND API. 414 */ 415 req_state->pwr_domain_state[ARM_PWR_LVL2] = ARM_LOCAL_STATE_RUN; 416 return rc; 417 } 418 419 /* 420 * Custom `translate_power_state_by_mpidr` handler for FVP. Unlike in the 421 * `fvp_validate_power_state`, we do not downgrade the system power 422 * domain level request in `power_state` as it will be used to query the 423 * PSCI_STAT_COUNT/RESIDENCY at the system power domain level. 424 */ 425 static int fvp_translate_power_state_by_mpidr(u_register_t mpidr, 426 unsigned int power_state, 427 psci_power_state_t *output_state) 428 { 429 return arm_validate_power_state(power_state, output_state); 430 } 431 432 /******************************************************************************* 433 * Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard 434 * platform layer will take care of registering the handlers with PSCI. 435 ******************************************************************************/ 436 plat_psci_ops_t plat_arm_psci_pm_ops = { 437 .cpu_standby = fvp_cpu_standby, 438 .pwr_domain_on = fvp_pwr_domain_on, 439 .pwr_domain_off = fvp_pwr_domain_off, 440 .pwr_domain_suspend = fvp_pwr_domain_suspend, 441 .pwr_domain_on_finish = fvp_pwr_domain_on_finish, 442 .pwr_domain_on_finish_late = fvp_pwr_domain_on_finish_late, 443 .pwr_domain_suspend_finish = fvp_pwr_domain_suspend_finish, 444 .system_off = fvp_system_off, 445 .system_reset = fvp_system_reset, 446 .validate_power_state = fvp_validate_power_state, 447 .validate_ns_entrypoint = arm_validate_psci_entrypoint, 448 .translate_power_state_by_mpidr = fvp_translate_power_state_by_mpidr, 449 .get_node_hw_state = fvp_node_hw_state, 450 #if !ARM_BL31_IN_DRAM 451 /* 452 * The TrustZone Controller is set up during the warmboot sequence after 453 * resuming the CPU from a SYSTEM_SUSPEND. If BL31 is located in SRAM 454 * this is not a problem but, if it is in TZC-secured DRAM, it tries to 455 * reconfigure the same memory it is running on, causing an exception. 456 */ 457 .get_sys_suspend_power_state = fvp_get_sys_suspend_power_state, 458 #endif 459 .mem_protect_chk = arm_psci_mem_protect_chk, 460 .read_mem_protect = arm_psci_read_mem_protect, 461 .write_mem_protect = arm_nor_psci_write_mem_protect, 462 }; 463 464 const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops) 465 { 466 return ops; 467 } 468