1 /* 2 * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch_helpers.h> 32 #include <arm_config.h> 33 #include <arm_gic.h> 34 #include <assert.h> 35 #include <debug.h> 36 #include <errno.h> 37 #include <mmio.h> 38 #include <platform.h> 39 #include <plat_arm.h> 40 #include <psci.h> 41 #include <v2m_def.h> 42 #include "drivers/pwrc/fvp_pwrc.h" 43 #include "fvp_def.h" 44 #include "fvp_private.h" 45 46 47 #if ARM_RECOM_STATE_ID_ENC 48 /* 49 * The table storing the valid idle power states. Ensure that the 50 * array entries are populated in ascending order of state-id to 51 * enable us to use binary search during power state validation. 52 * The table must be terminated by a NULL entry. 53 */ 54 const unsigned int arm_pm_idle_states[] = { 55 /* State-id - 0x01 */ 56 arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_RET, 57 ARM_PWR_LVL0, PSTATE_TYPE_STANDBY), 58 /* State-id - 0x02 */ 59 arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_OFF, 60 ARM_PWR_LVL0, PSTATE_TYPE_POWERDOWN), 61 /* State-id - 0x22 */ 62 arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_OFF, ARM_LOCAL_STATE_OFF, 63 ARM_PWR_LVL1, PSTATE_TYPE_POWERDOWN), 64 0, 65 }; 66 #endif 67 68 /******************************************************************************* 69 * Function which implements the common FVP specific operations to power down a 70 * cpu in response to a CPU_OFF or CPU_SUSPEND request. 71 ******************************************************************************/ 72 static void fvp_cpu_pwrdwn_common(void) 73 { 74 /* Prevent interrupts from spuriously waking up this cpu */ 75 arm_gic_cpuif_deactivate(); 76 77 /* Program the power controller to power off this cpu. */ 78 fvp_pwrc_write_ppoffr(read_mpidr_el1()); 79 } 80 81 /******************************************************************************* 82 * Function which implements the common FVP specific operations to power down a 83 * cluster in response to a CPU_OFF or CPU_SUSPEND request. 84 ******************************************************************************/ 85 static void fvp_cluster_pwrdwn_common(void) 86 { 87 uint64_t mpidr = read_mpidr_el1(); 88 89 /* Disable coherency if this cluster is to be turned off */ 90 fvp_cci_disable(); 91 92 /* Program the power controller to turn the cluster off */ 93 fvp_pwrc_write_pcoffr(mpidr); 94 } 95 96 /******************************************************************************* 97 * FVP handler called when a CPU is about to enter standby. 98 ******************************************************************************/ 99 void fvp_cpu_standby(plat_local_state_t cpu_state) 100 { 101 102 assert(cpu_state == ARM_LOCAL_STATE_RET); 103 104 /* 105 * Enter standby state 106 * dsb is good practice before using wfi to enter low power states 107 */ 108 dsb(); 109 wfi(); 110 } 111 112 /******************************************************************************* 113 * FVP handler called when a power domain is about to be turned on. The 114 * mpidr determines the CPU to be turned on. 115 ******************************************************************************/ 116 int fvp_pwr_domain_on(u_register_t mpidr) 117 { 118 int rc = PSCI_E_SUCCESS; 119 unsigned int psysr; 120 121 /* 122 * Ensure that we do not cancel an inflight power off request 123 * for the target cpu. That would leave it in a zombie wfi. 124 * Wait for it to power off, program the jump address for the 125 * target cpu and then program the power controller to turn 126 * that cpu on 127 */ 128 do { 129 psysr = fvp_pwrc_read_psysr(mpidr); 130 } while (psysr & PSYSR_AFF_L0); 131 132 fvp_pwrc_write_pponr(mpidr); 133 return rc; 134 } 135 136 /******************************************************************************* 137 * FVP handler called when a power domain is about to be turned off. The 138 * target_state encodes the power state that each level should transition to. 139 ******************************************************************************/ 140 void fvp_pwr_domain_off(const psci_power_state_t *target_state) 141 { 142 assert(target_state->pwr_domain_state[ARM_PWR_LVL0] == 143 ARM_LOCAL_STATE_OFF); 144 145 /* 146 * If execution reaches this stage then this power domain will be 147 * suspended. Perform at least the cpu specific actions followed 148 * by the cluster specific operations if applicable. 149 */ 150 fvp_cpu_pwrdwn_common(); 151 152 if (target_state->pwr_domain_state[ARM_PWR_LVL1] == 153 ARM_LOCAL_STATE_OFF) 154 fvp_cluster_pwrdwn_common(); 155 156 } 157 158 /******************************************************************************* 159 * FVP handler called when a power domain is about to be suspended. The 160 * target_state encodes the power state that each level should transition to. 161 ******************************************************************************/ 162 void fvp_pwr_domain_suspend(const psci_power_state_t *target_state) 163 { 164 unsigned long mpidr; 165 166 /* 167 * FVP has retention only at cpu level. Just return 168 * as nothing is to be done for retention. 169 */ 170 if (target_state->pwr_domain_state[ARM_PWR_LVL0] == 171 ARM_LOCAL_STATE_RET) 172 return; 173 174 assert(target_state->pwr_domain_state[ARM_PWR_LVL0] == 175 ARM_LOCAL_STATE_OFF); 176 177 /* Get the mpidr for this cpu */ 178 mpidr = read_mpidr_el1(); 179 180 /* Program the power controller to enable wakeup interrupts. */ 181 fvp_pwrc_set_wen(mpidr); 182 183 /* Perform the common cpu specific operations */ 184 fvp_cpu_pwrdwn_common(); 185 186 /* Perform the common cluster specific operations */ 187 if (target_state->pwr_domain_state[ARM_PWR_LVL1] == 188 ARM_LOCAL_STATE_OFF) 189 fvp_cluster_pwrdwn_common(); 190 } 191 192 /******************************************************************************* 193 * FVP handler called when a power domain has just been powered on after 194 * being turned off earlier. The target_state encodes the low power state that 195 * each level has woken up from. 196 ******************************************************************************/ 197 void fvp_pwr_domain_on_finish(const psci_power_state_t *target_state) 198 { 199 unsigned long mpidr; 200 201 assert(target_state->pwr_domain_state[ARM_PWR_LVL0] == 202 ARM_LOCAL_STATE_OFF); 203 204 /* Get the mpidr for this cpu */ 205 mpidr = read_mpidr_el1(); 206 207 /* Perform the common cluster specific operations */ 208 if (target_state->pwr_domain_state[ARM_PWR_LVL1] == 209 ARM_LOCAL_STATE_OFF) { 210 /* 211 * This CPU might have woken up whilst the cluster was 212 * attempting to power down. In this case the FVP power 213 * controller will have a pending cluster power off request 214 * which needs to be cleared by writing to the PPONR register. 215 * This prevents the power controller from interpreting a 216 * subsequent entry of this cpu into a simple wfi as a power 217 * down request. 218 */ 219 fvp_pwrc_write_pponr(mpidr); 220 221 /* Enable coherency if this cluster was off */ 222 fvp_cci_enable(); 223 } 224 225 /* 226 * Clear PWKUPR.WEN bit to ensure interrupts do not interfere 227 * with a cpu power down unless the bit is set again 228 */ 229 fvp_pwrc_clr_wen(mpidr); 230 231 /* Enable the gic cpu interface */ 232 arm_gic_cpuif_setup(); 233 234 /* TODO: This setup is needed only after a cold boot */ 235 arm_gic_pcpu_distif_setup(); 236 } 237 238 /******************************************************************************* 239 * FVP handler called when a power domain has just been powered on after 240 * having been suspended earlier. The target_state encodes the low power state 241 * that each level has woken up from. 242 * TODO: At the moment we reuse the on finisher and reinitialize the secure 243 * context. Need to implement a separate suspend finisher. 244 ******************************************************************************/ 245 void fvp_pwr_domain_suspend_finish(const psci_power_state_t *target_state) 246 { 247 /* 248 * Nothing to be done on waking up from retention from CPU level. 249 */ 250 if (target_state->pwr_domain_state[ARM_PWR_LVL0] == 251 ARM_LOCAL_STATE_RET) 252 return; 253 254 fvp_pwr_domain_on_finish(target_state); 255 } 256 257 /******************************************************************************* 258 * FVP handlers to shutdown/reboot the system 259 ******************************************************************************/ 260 static void __dead2 fvp_system_off(void) 261 { 262 /* Write the System Configuration Control Register */ 263 mmio_write_32(V2M_SYSREGS_BASE + V2M_SYS_CFGCTRL, 264 V2M_CFGCTRL_START | 265 V2M_CFGCTRL_RW | 266 V2M_CFGCTRL_FUNC(V2M_FUNC_SHUTDOWN)); 267 wfi(); 268 ERROR("FVP System Off: operation not handled.\n"); 269 panic(); 270 } 271 272 static void __dead2 fvp_system_reset(void) 273 { 274 /* Write the System Configuration Control Register */ 275 mmio_write_32(V2M_SYSREGS_BASE + V2M_SYS_CFGCTRL, 276 V2M_CFGCTRL_START | 277 V2M_CFGCTRL_RW | 278 V2M_CFGCTRL_FUNC(V2M_FUNC_REBOOT)); 279 wfi(); 280 ERROR("FVP System Reset: operation not handled.\n"); 281 panic(); 282 } 283 284 /******************************************************************************* 285 * Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard 286 * platform layer will take care of registering the handlers with PSCI. 287 ******************************************************************************/ 288 const plat_psci_ops_t plat_arm_psci_pm_ops = { 289 .cpu_standby = fvp_cpu_standby, 290 .pwr_domain_on = fvp_pwr_domain_on, 291 .pwr_domain_off = fvp_pwr_domain_off, 292 .pwr_domain_suspend = fvp_pwr_domain_suspend, 293 .pwr_domain_on_finish = fvp_pwr_domain_on_finish, 294 .pwr_domain_suspend_finish = fvp_pwr_domain_suspend_finish, 295 .system_off = fvp_system_off, 296 .system_reset = fvp_system_reset, 297 .validate_power_state = arm_validate_power_state, 298 .validate_ns_entrypoint = arm_validate_ns_entrypoint 299 }; 300