1 /* 2 * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch_helpers.h> 32 #include <arm_config.h> 33 #include <assert.h> 34 #include <debug.h> 35 #include <errno.h> 36 #include <mmio.h> 37 #include <platform.h> 38 #include <plat_arm.h> 39 #include <psci.h> 40 #include <v2m_def.h> 41 #include "drivers/pwrc/fvp_pwrc.h" 42 #include "fvp_def.h" 43 #include "fvp_private.h" 44 45 46 #if ARM_RECOM_STATE_ID_ENC 47 /* 48 * The table storing the valid idle power states. Ensure that the 49 * array entries are populated in ascending order of state-id to 50 * enable us to use binary search during power state validation. 51 * The table must be terminated by a NULL entry. 52 */ 53 const unsigned int arm_pm_idle_states[] = { 54 /* State-id - 0x01 */ 55 arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_RET, 56 ARM_PWR_LVL0, PSTATE_TYPE_STANDBY), 57 /* State-id - 0x02 */ 58 arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_OFF, 59 ARM_PWR_LVL0, PSTATE_TYPE_POWERDOWN), 60 /* State-id - 0x22 */ 61 arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_OFF, ARM_LOCAL_STATE_OFF, 62 ARM_PWR_LVL1, PSTATE_TYPE_POWERDOWN), 63 0, 64 }; 65 #endif 66 67 /******************************************************************************* 68 * Function which implements the common FVP specific operations to power down a 69 * cluster in response to a CPU_OFF or CPU_SUSPEND request. 70 ******************************************************************************/ 71 static void fvp_cluster_pwrdwn_common(void) 72 { 73 uint64_t mpidr = read_mpidr_el1(); 74 75 /* Disable coherency if this cluster is to be turned off */ 76 fvp_interconnect_disable(); 77 78 /* Program the power controller to turn the cluster off */ 79 fvp_pwrc_write_pcoffr(mpidr); 80 } 81 82 static void fvp_power_domain_on_finish_common(const psci_power_state_t *target_state) 83 { 84 unsigned long mpidr; 85 86 assert(target_state->pwr_domain_state[ARM_PWR_LVL0] == 87 ARM_LOCAL_STATE_OFF); 88 89 /* Get the mpidr for this cpu */ 90 mpidr = read_mpidr_el1(); 91 92 /* Perform the common cluster specific operations */ 93 if (target_state->pwr_domain_state[ARM_PWR_LVL1] == 94 ARM_LOCAL_STATE_OFF) { 95 /* 96 * This CPU might have woken up whilst the cluster was 97 * attempting to power down. In this case the FVP power 98 * controller will have a pending cluster power off request 99 * which needs to be cleared by writing to the PPONR register. 100 * This prevents the power controller from interpreting a 101 * subsequent entry of this cpu into a simple wfi as a power 102 * down request. 103 */ 104 fvp_pwrc_write_pponr(mpidr); 105 106 /* Enable coherency if this cluster was off */ 107 fvp_interconnect_enable(); 108 } 109 110 /* 111 * Clear PWKUPR.WEN bit to ensure interrupts do not interfere 112 * with a cpu power down unless the bit is set again 113 */ 114 fvp_pwrc_clr_wen(mpidr); 115 } 116 117 118 /******************************************************************************* 119 * FVP handler called when a CPU is about to enter standby. 120 ******************************************************************************/ 121 void fvp_cpu_standby(plat_local_state_t cpu_state) 122 { 123 124 assert(cpu_state == ARM_LOCAL_STATE_RET); 125 126 /* 127 * Enter standby state 128 * dsb is good practice before using wfi to enter low power states 129 */ 130 dsb(); 131 wfi(); 132 } 133 134 /******************************************************************************* 135 * FVP handler called when a power domain is about to be turned on. The 136 * mpidr determines the CPU to be turned on. 137 ******************************************************************************/ 138 int fvp_pwr_domain_on(u_register_t mpidr) 139 { 140 int rc = PSCI_E_SUCCESS; 141 unsigned int psysr; 142 143 /* 144 * Ensure that we do not cancel an inflight power off request for the 145 * target cpu. That would leave it in a zombie wfi. Wait for it to power 146 * off and then program the power controller to turn that CPU on. 147 */ 148 do { 149 psysr = fvp_pwrc_read_psysr(mpidr); 150 } while (psysr & PSYSR_AFF_L0); 151 152 fvp_pwrc_write_pponr(mpidr); 153 return rc; 154 } 155 156 /******************************************************************************* 157 * FVP handler called when a power domain is about to be turned off. The 158 * target_state encodes the power state that each level should transition to. 159 ******************************************************************************/ 160 void fvp_pwr_domain_off(const psci_power_state_t *target_state) 161 { 162 assert(target_state->pwr_domain_state[ARM_PWR_LVL0] == 163 ARM_LOCAL_STATE_OFF); 164 165 /* 166 * If execution reaches this stage then this power domain will be 167 * suspended. Perform at least the cpu specific actions followed 168 * by the cluster specific operations if applicable. 169 */ 170 171 /* Prevent interrupts from spuriously waking up this cpu */ 172 plat_arm_gic_cpuif_disable(); 173 174 /* Turn redistributor off */ 175 plat_arm_gic_redistif_off(); 176 177 /* Program the power controller to power off this cpu. */ 178 fvp_pwrc_write_ppoffr(read_mpidr_el1()); 179 180 if (target_state->pwr_domain_state[ARM_PWR_LVL1] == 181 ARM_LOCAL_STATE_OFF) 182 fvp_cluster_pwrdwn_common(); 183 184 } 185 186 /******************************************************************************* 187 * FVP handler called when a power domain is about to be suspended. The 188 * target_state encodes the power state that each level should transition to. 189 ******************************************************************************/ 190 void fvp_pwr_domain_suspend(const psci_power_state_t *target_state) 191 { 192 unsigned long mpidr; 193 194 /* 195 * FVP has retention only at cpu level. Just return 196 * as nothing is to be done for retention. 197 */ 198 if (target_state->pwr_domain_state[ARM_PWR_LVL0] == 199 ARM_LOCAL_STATE_RET) 200 return; 201 202 assert(target_state->pwr_domain_state[ARM_PWR_LVL0] == 203 ARM_LOCAL_STATE_OFF); 204 205 /* Get the mpidr for this cpu */ 206 mpidr = read_mpidr_el1(); 207 208 /* Program the power controller to enable wakeup interrupts. */ 209 fvp_pwrc_set_wen(mpidr); 210 211 /* Prevent interrupts from spuriously waking up this cpu */ 212 plat_arm_gic_cpuif_disable(); 213 214 /* 215 * The Redistributor is not powered off as it can potentially prevent 216 * wake up events reaching the CPUIF and/or might lead to losing 217 * register context. 218 */ 219 220 /* Program the power controller to power off this cpu. */ 221 fvp_pwrc_write_ppoffr(read_mpidr_el1()); 222 223 /* Perform the common cluster specific operations */ 224 if (target_state->pwr_domain_state[ARM_PWR_LVL1] == 225 ARM_LOCAL_STATE_OFF) 226 fvp_cluster_pwrdwn_common(); 227 } 228 229 /******************************************************************************* 230 * FVP handler called when a power domain has just been powered on after 231 * being turned off earlier. The target_state encodes the low power state that 232 * each level has woken up from. 233 ******************************************************************************/ 234 void fvp_pwr_domain_on_finish(const psci_power_state_t *target_state) 235 { 236 fvp_power_domain_on_finish_common(target_state); 237 238 /* Enable the gic cpu interface */ 239 plat_arm_gic_pcpu_init(); 240 241 /* Program the gic per-cpu distributor or re-distributor interface */ 242 plat_arm_gic_cpuif_enable(); 243 } 244 245 /******************************************************************************* 246 * FVP handler called when a power domain has just been powered on after 247 * having been suspended earlier. The target_state encodes the low power state 248 * that each level has woken up from. 249 * TODO: At the moment we reuse the on finisher and reinitialize the secure 250 * context. Need to implement a separate suspend finisher. 251 ******************************************************************************/ 252 void fvp_pwr_domain_suspend_finish(const psci_power_state_t *target_state) 253 { 254 /* 255 * Nothing to be done on waking up from retention from CPU level. 256 */ 257 if (target_state->pwr_domain_state[ARM_PWR_LVL0] == 258 ARM_LOCAL_STATE_RET) 259 return; 260 261 fvp_power_domain_on_finish_common(target_state); 262 263 /* Enable the gic cpu interface */ 264 plat_arm_gic_cpuif_enable(); 265 } 266 267 /******************************************************************************* 268 * FVP handlers to shutdown/reboot the system 269 ******************************************************************************/ 270 static void __dead2 fvp_system_off(void) 271 { 272 /* Write the System Configuration Control Register */ 273 mmio_write_32(V2M_SYSREGS_BASE + V2M_SYS_CFGCTRL, 274 V2M_CFGCTRL_START | 275 V2M_CFGCTRL_RW | 276 V2M_CFGCTRL_FUNC(V2M_FUNC_SHUTDOWN)); 277 wfi(); 278 ERROR("FVP System Off: operation not handled.\n"); 279 panic(); 280 } 281 282 static void __dead2 fvp_system_reset(void) 283 { 284 /* Write the System Configuration Control Register */ 285 mmio_write_32(V2M_SYSREGS_BASE + V2M_SYS_CFGCTRL, 286 V2M_CFGCTRL_START | 287 V2M_CFGCTRL_RW | 288 V2M_CFGCTRL_FUNC(V2M_FUNC_REBOOT)); 289 wfi(); 290 ERROR("FVP System Reset: operation not handled.\n"); 291 panic(); 292 } 293 294 static int fvp_node_hw_state(u_register_t target_cpu, 295 unsigned int power_level) 296 { 297 unsigned int psysr; 298 int ret; 299 300 /* 301 * The format of 'power_level' is implementation-defined, but 0 must 302 * mean a CPU. We also allow 1 to denote the cluster 303 */ 304 if (power_level != ARM_PWR_LVL0 && power_level != ARM_PWR_LVL1) 305 return PSCI_E_INVALID_PARAMS; 306 307 /* 308 * Read the status of the given MPDIR from FVP power controller. The 309 * power controller only gives us on/off status, so map that to expected 310 * return values of the PSCI call 311 */ 312 psysr = fvp_pwrc_read_psysr(target_cpu); 313 if (psysr == PSYSR_INVALID) 314 return PSCI_E_INVALID_PARAMS; 315 316 switch (power_level) { 317 case ARM_PWR_LVL0: 318 ret = (psysr & PSYSR_AFF_L0) ? HW_ON : HW_OFF; 319 break; 320 case ARM_PWR_LVL1: 321 ret = (psysr & PSYSR_AFF_L1) ? HW_ON : HW_OFF; 322 break; 323 default: 324 assert(0); 325 } 326 327 return ret; 328 } 329 330 /******************************************************************************* 331 * Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard 332 * platform layer will take care of registering the handlers with PSCI. 333 ******************************************************************************/ 334 plat_psci_ops_t plat_arm_psci_pm_ops = { 335 .cpu_standby = fvp_cpu_standby, 336 .pwr_domain_on = fvp_pwr_domain_on, 337 .pwr_domain_off = fvp_pwr_domain_off, 338 .pwr_domain_suspend = fvp_pwr_domain_suspend, 339 .pwr_domain_on_finish = fvp_pwr_domain_on_finish, 340 .pwr_domain_suspend_finish = fvp_pwr_domain_suspend_finish, 341 .system_off = fvp_system_off, 342 .system_reset = fvp_system_reset, 343 .validate_power_state = arm_validate_power_state, 344 .validate_ns_entrypoint = arm_validate_ns_entrypoint, 345 .get_node_hw_state = fvp_node_hw_state 346 }; 347