1 /* 2 * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch_helpers.h> 32 #include <arm_config.h> 33 #include <assert.h> 34 #include <debug.h> 35 #include <errno.h> 36 #include <mmio.h> 37 #include <platform.h> 38 #include <plat_arm.h> 39 #include <psci.h> 40 #include <v2m_def.h> 41 #include "drivers/pwrc/fvp_pwrc.h" 42 #include "fvp_def.h" 43 #include "fvp_private.h" 44 45 46 #if ARM_RECOM_STATE_ID_ENC 47 /* 48 * The table storing the valid idle power states. Ensure that the 49 * array entries are populated in ascending order of state-id to 50 * enable us to use binary search during power state validation. 51 * The table must be terminated by a NULL entry. 52 */ 53 const unsigned int arm_pm_idle_states[] = { 54 /* State-id - 0x01 */ 55 arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_RET, 56 ARM_PWR_LVL0, PSTATE_TYPE_STANDBY), 57 /* State-id - 0x02 */ 58 arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_OFF, 59 ARM_PWR_LVL0, PSTATE_TYPE_POWERDOWN), 60 /* State-id - 0x22 */ 61 arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_OFF, ARM_LOCAL_STATE_OFF, 62 ARM_PWR_LVL1, PSTATE_TYPE_POWERDOWN), 63 0, 64 }; 65 #endif 66 67 /******************************************************************************* 68 * Function which implements the common FVP specific operations to power down a 69 * cpu in response to a CPU_OFF or CPU_SUSPEND request. 70 ******************************************************************************/ 71 static void fvp_cpu_pwrdwn_common(void) 72 { 73 /* Prevent interrupts from spuriously waking up this cpu */ 74 plat_arm_gic_cpuif_disable(); 75 76 /* Program the power controller to power off this cpu. */ 77 fvp_pwrc_write_ppoffr(read_mpidr_el1()); 78 } 79 80 /******************************************************************************* 81 * Function which implements the common FVP specific operations to power down a 82 * cluster in response to a CPU_OFF or CPU_SUSPEND request. 83 ******************************************************************************/ 84 static void fvp_cluster_pwrdwn_common(void) 85 { 86 uint64_t mpidr = read_mpidr_el1(); 87 88 /* Disable coherency if this cluster is to be turned off */ 89 fvp_cci_disable(); 90 91 /* Program the power controller to turn the cluster off */ 92 fvp_pwrc_write_pcoffr(mpidr); 93 } 94 95 static void fvp_power_domain_on_finish_common(const psci_power_state_t *target_state) 96 { 97 unsigned long mpidr; 98 99 assert(target_state->pwr_domain_state[ARM_PWR_LVL0] == 100 ARM_LOCAL_STATE_OFF); 101 102 /* Get the mpidr for this cpu */ 103 mpidr = read_mpidr_el1(); 104 105 /* Perform the common cluster specific operations */ 106 if (target_state->pwr_domain_state[ARM_PWR_LVL1] == 107 ARM_LOCAL_STATE_OFF) { 108 /* 109 * This CPU might have woken up whilst the cluster was 110 * attempting to power down. In this case the FVP power 111 * controller will have a pending cluster power off request 112 * which needs to be cleared by writing to the PPONR register. 113 * This prevents the power controller from interpreting a 114 * subsequent entry of this cpu into a simple wfi as a power 115 * down request. 116 */ 117 fvp_pwrc_write_pponr(mpidr); 118 119 /* Enable coherency if this cluster was off */ 120 fvp_cci_enable(); 121 } 122 123 /* 124 * Clear PWKUPR.WEN bit to ensure interrupts do not interfere 125 * with a cpu power down unless the bit is set again 126 */ 127 fvp_pwrc_clr_wen(mpidr); 128 } 129 130 131 /******************************************************************************* 132 * FVP handler called when a CPU is about to enter standby. 133 ******************************************************************************/ 134 void fvp_cpu_standby(plat_local_state_t cpu_state) 135 { 136 137 assert(cpu_state == ARM_LOCAL_STATE_RET); 138 139 /* 140 * Enter standby state 141 * dsb is good practice before using wfi to enter low power states 142 */ 143 dsb(); 144 wfi(); 145 } 146 147 /******************************************************************************* 148 * FVP handler called when a power domain is about to be turned on. The 149 * mpidr determines the CPU to be turned on. 150 ******************************************************************************/ 151 int fvp_pwr_domain_on(u_register_t mpidr) 152 { 153 int rc = PSCI_E_SUCCESS; 154 unsigned int psysr; 155 156 /* 157 * Ensure that we do not cancel an inflight power off request 158 * for the target cpu. That would leave it in a zombie wfi. 159 * Wait for it to power off, program the jump address for the 160 * target cpu and then program the power controller to turn 161 * that cpu on 162 */ 163 do { 164 psysr = fvp_pwrc_read_psysr(mpidr); 165 } while (psysr & PSYSR_AFF_L0); 166 167 fvp_pwrc_write_pponr(mpidr); 168 return rc; 169 } 170 171 /******************************************************************************* 172 * FVP handler called when a power domain is about to be turned off. The 173 * target_state encodes the power state that each level should transition to. 174 ******************************************************************************/ 175 void fvp_pwr_domain_off(const psci_power_state_t *target_state) 176 { 177 assert(target_state->pwr_domain_state[ARM_PWR_LVL0] == 178 ARM_LOCAL_STATE_OFF); 179 180 /* 181 * If execution reaches this stage then this power domain will be 182 * suspended. Perform at least the cpu specific actions followed 183 * by the cluster specific operations if applicable. 184 */ 185 fvp_cpu_pwrdwn_common(); 186 187 if (target_state->pwr_domain_state[ARM_PWR_LVL1] == 188 ARM_LOCAL_STATE_OFF) 189 fvp_cluster_pwrdwn_common(); 190 191 } 192 193 /******************************************************************************* 194 * FVP handler called when a power domain is about to be suspended. The 195 * target_state encodes the power state that each level should transition to. 196 ******************************************************************************/ 197 void fvp_pwr_domain_suspend(const psci_power_state_t *target_state) 198 { 199 unsigned long mpidr; 200 201 /* 202 * FVP has retention only at cpu level. Just return 203 * as nothing is to be done for retention. 204 */ 205 if (target_state->pwr_domain_state[ARM_PWR_LVL0] == 206 ARM_LOCAL_STATE_RET) 207 return; 208 209 assert(target_state->pwr_domain_state[ARM_PWR_LVL0] == 210 ARM_LOCAL_STATE_OFF); 211 212 /* Get the mpidr for this cpu */ 213 mpidr = read_mpidr_el1(); 214 215 /* Program the power controller to enable wakeup interrupts. */ 216 fvp_pwrc_set_wen(mpidr); 217 218 /* Perform the common cpu specific operations */ 219 fvp_cpu_pwrdwn_common(); 220 221 /* Perform the common cluster specific operations */ 222 if (target_state->pwr_domain_state[ARM_PWR_LVL1] == 223 ARM_LOCAL_STATE_OFF) 224 fvp_cluster_pwrdwn_common(); 225 } 226 227 /******************************************************************************* 228 * FVP handler called when a power domain has just been powered on after 229 * being turned off earlier. The target_state encodes the low power state that 230 * each level has woken up from. 231 ******************************************************************************/ 232 void fvp_pwr_domain_on_finish(const psci_power_state_t *target_state) 233 { 234 fvp_power_domain_on_finish_common(target_state); 235 236 /* Enable the gic cpu interface */ 237 plat_arm_gic_pcpu_init(); 238 239 /* Program the gic per-cpu distributor or re-distributor interface */ 240 plat_arm_gic_cpuif_enable(); 241 } 242 243 /******************************************************************************* 244 * FVP handler called when a power domain has just been powered on after 245 * having been suspended earlier. The target_state encodes the low power state 246 * that each level has woken up from. 247 * TODO: At the moment we reuse the on finisher and reinitialize the secure 248 * context. Need to implement a separate suspend finisher. 249 ******************************************************************************/ 250 void fvp_pwr_domain_suspend_finish(const psci_power_state_t *target_state) 251 { 252 /* 253 * Nothing to be done on waking up from retention from CPU level. 254 */ 255 if (target_state->pwr_domain_state[ARM_PWR_LVL0] == 256 ARM_LOCAL_STATE_RET) 257 return; 258 259 fvp_power_domain_on_finish_common(target_state); 260 261 /* Enable the gic cpu interface */ 262 plat_arm_gic_cpuif_enable(); 263 } 264 265 /******************************************************************************* 266 * FVP handlers to shutdown/reboot the system 267 ******************************************************************************/ 268 static void __dead2 fvp_system_off(void) 269 { 270 /* Write the System Configuration Control Register */ 271 mmio_write_32(V2M_SYSREGS_BASE + V2M_SYS_CFGCTRL, 272 V2M_CFGCTRL_START | 273 V2M_CFGCTRL_RW | 274 V2M_CFGCTRL_FUNC(V2M_FUNC_SHUTDOWN)); 275 wfi(); 276 ERROR("FVP System Off: operation not handled.\n"); 277 panic(); 278 } 279 280 static void __dead2 fvp_system_reset(void) 281 { 282 /* Write the System Configuration Control Register */ 283 mmio_write_32(V2M_SYSREGS_BASE + V2M_SYS_CFGCTRL, 284 V2M_CFGCTRL_START | 285 V2M_CFGCTRL_RW | 286 V2M_CFGCTRL_FUNC(V2M_FUNC_REBOOT)); 287 wfi(); 288 ERROR("FVP System Reset: operation not handled.\n"); 289 panic(); 290 } 291 292 /******************************************************************************* 293 * Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard 294 * platform layer will take care of registering the handlers with PSCI. 295 ******************************************************************************/ 296 const plat_psci_ops_t plat_arm_psci_pm_ops = { 297 .cpu_standby = fvp_cpu_standby, 298 .pwr_domain_on = fvp_pwr_domain_on, 299 .pwr_domain_off = fvp_pwr_domain_off, 300 .pwr_domain_suspend = fvp_pwr_domain_suspend, 301 .pwr_domain_on_finish = fvp_pwr_domain_on_finish, 302 .pwr_domain_suspend_finish = fvp_pwr_domain_suspend_finish, 303 .system_off = fvp_system_off, 304 .system_reset = fvp_system_reset, 305 .validate_power_state = arm_validate_power_state, 306 .validate_ns_entrypoint = arm_validate_ns_entrypoint 307 }; 308