1 /* 2 * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <arm_config.h> 9 #include <assert.h> 10 #include <debug.h> 11 #include <errno.h> 12 #include <gicv3.h> 13 #include <mmio.h> 14 #include <plat_arm.h> 15 #include <platform.h> 16 #include <psci.h> 17 #include <spe.h> 18 #include <v2m_def.h> 19 #include "../../../../drivers/arm/gic/v3/gicv3_private.h" 20 #include "drivers/pwrc/fvp_pwrc.h" 21 #include "fvp_def.h" 22 #include "fvp_private.h" 23 24 25 #if ARM_RECOM_STATE_ID_ENC 26 /* 27 * The table storing the valid idle power states. Ensure that the 28 * array entries are populated in ascending order of state-id to 29 * enable us to use binary search during power state validation. 30 * The table must be terminated by a NULL entry. 31 */ 32 const unsigned int arm_pm_idle_states[] = { 33 /* State-id - 0x01 */ 34 arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_RET, 35 ARM_PWR_LVL0, PSTATE_TYPE_STANDBY), 36 /* State-id - 0x02 */ 37 arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_OFF, 38 ARM_PWR_LVL0, PSTATE_TYPE_POWERDOWN), 39 /* State-id - 0x22 */ 40 arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_OFF, ARM_LOCAL_STATE_OFF, 41 ARM_PWR_LVL1, PSTATE_TYPE_POWERDOWN), 42 /* State-id - 0x222 */ 43 arm_make_pwrstate_lvl2(ARM_LOCAL_STATE_OFF, ARM_LOCAL_STATE_OFF, 44 ARM_LOCAL_STATE_OFF, ARM_PWR_LVL2, PSTATE_TYPE_POWERDOWN), 45 0, 46 }; 47 #endif 48 49 /******************************************************************************* 50 * Function which implements the common FVP specific operations to power down a 51 * cluster in response to a CPU_OFF or CPU_SUSPEND request. 52 ******************************************************************************/ 53 static void fvp_cluster_pwrdwn_common(void) 54 { 55 uint64_t mpidr = read_mpidr_el1(); 56 57 #if ENABLE_SPE_FOR_LOWER_ELS 58 /* 59 * On power down we need to disable statistical profiling extensions 60 * before exiting coherency. 61 */ 62 spe_disable(); 63 #endif 64 65 /* Disable coherency if this cluster is to be turned off */ 66 fvp_interconnect_disable(); 67 68 /* Program the power controller to turn the cluster off */ 69 fvp_pwrc_write_pcoffr(mpidr); 70 } 71 72 /* 73 * Empty implementation of these hooks avoid setting the GICR_WAKER.Sleep bit 74 * on ARM GICv3 implementations on FVP. This is required, because FVP does not 75 * support SYSTEM_SUSPEND and it is `faked` in firmware. Hence, for wake up 76 * from `fake` system suspend the GIC must not be powered off. 77 */ 78 void arm_gicv3_distif_pre_save(unsigned int rdist_proc_num) 79 {} 80 81 void arm_gicv3_distif_post_restore(unsigned int rdist_proc_num) 82 {} 83 84 static void fvp_power_domain_on_finish_common(const psci_power_state_t *target_state) 85 { 86 unsigned long mpidr; 87 88 assert(target_state->pwr_domain_state[ARM_PWR_LVL0] == 89 ARM_LOCAL_STATE_OFF); 90 91 /* Get the mpidr for this cpu */ 92 mpidr = read_mpidr_el1(); 93 94 /* Perform the common cluster specific operations */ 95 if (target_state->pwr_domain_state[ARM_PWR_LVL1] == 96 ARM_LOCAL_STATE_OFF) { 97 /* 98 * This CPU might have woken up whilst the cluster was 99 * attempting to power down. In this case the FVP power 100 * controller will have a pending cluster power off request 101 * which needs to be cleared by writing to the PPONR register. 102 * This prevents the power controller from interpreting a 103 * subsequent entry of this cpu into a simple wfi as a power 104 * down request. 105 */ 106 fvp_pwrc_write_pponr(mpidr); 107 108 /* Enable coherency if this cluster was off */ 109 fvp_interconnect_enable(); 110 } 111 /* Perform the common system specific operations */ 112 if (target_state->pwr_domain_state[ARM_PWR_LVL2] == 113 ARM_LOCAL_STATE_OFF) 114 arm_system_pwr_domain_resume(); 115 116 /* 117 * Clear PWKUPR.WEN bit to ensure interrupts do not interfere 118 * with a cpu power down unless the bit is set again 119 */ 120 fvp_pwrc_clr_wen(mpidr); 121 } 122 123 124 /******************************************************************************* 125 * FVP handler called when a CPU is about to enter standby. 126 ******************************************************************************/ 127 static void fvp_cpu_standby(plat_local_state_t cpu_state) 128 { 129 130 assert(cpu_state == ARM_LOCAL_STATE_RET); 131 132 /* 133 * Enter standby state 134 * dsb is good practice before using wfi to enter low power states 135 */ 136 dsb(); 137 wfi(); 138 } 139 140 /******************************************************************************* 141 * FVP handler called when a power domain is about to be turned on. The 142 * mpidr determines the CPU to be turned on. 143 ******************************************************************************/ 144 static int fvp_pwr_domain_on(u_register_t mpidr) 145 { 146 int rc = PSCI_E_SUCCESS; 147 unsigned int psysr; 148 149 /* 150 * Ensure that we do not cancel an inflight power off request for the 151 * target cpu. That would leave it in a zombie wfi. Wait for it to power 152 * off and then program the power controller to turn that CPU on. 153 */ 154 do { 155 psysr = fvp_pwrc_read_psysr(mpidr); 156 } while ((psysr & PSYSR_AFF_L0) != 0U); 157 158 fvp_pwrc_write_pponr(mpidr); 159 return rc; 160 } 161 162 /******************************************************************************* 163 * FVP handler called when a power domain is about to be turned off. The 164 * target_state encodes the power state that each level should transition to. 165 ******************************************************************************/ 166 static void fvp_pwr_domain_off(const psci_power_state_t *target_state) 167 { 168 assert(target_state->pwr_domain_state[ARM_PWR_LVL0] == 169 ARM_LOCAL_STATE_OFF); 170 171 /* 172 * If execution reaches this stage then this power domain will be 173 * suspended. Perform at least the cpu specific actions followed 174 * by the cluster specific operations if applicable. 175 */ 176 177 /* Prevent interrupts from spuriously waking up this cpu */ 178 plat_arm_gic_cpuif_disable(); 179 180 /* Turn redistributor off */ 181 plat_arm_gic_redistif_off(); 182 183 /* Program the power controller to power off this cpu. */ 184 fvp_pwrc_write_ppoffr(read_mpidr_el1()); 185 186 if (target_state->pwr_domain_state[ARM_PWR_LVL1] == 187 ARM_LOCAL_STATE_OFF) 188 fvp_cluster_pwrdwn_common(); 189 190 } 191 192 /******************************************************************************* 193 * FVP handler called when a power domain is about to be suspended. The 194 * target_state encodes the power state that each level should transition to. 195 ******************************************************************************/ 196 static void fvp_pwr_domain_suspend(const psci_power_state_t *target_state) 197 { 198 unsigned long mpidr; 199 200 /* 201 * FVP has retention only at cpu level. Just return 202 * as nothing is to be done for retention. 203 */ 204 if (target_state->pwr_domain_state[ARM_PWR_LVL0] == 205 ARM_LOCAL_STATE_RET) 206 return; 207 208 assert(target_state->pwr_domain_state[ARM_PWR_LVL0] == 209 ARM_LOCAL_STATE_OFF); 210 211 /* Get the mpidr for this cpu */ 212 mpidr = read_mpidr_el1(); 213 214 /* Program the power controller to enable wakeup interrupts. */ 215 fvp_pwrc_set_wen(mpidr); 216 217 /* Prevent interrupts from spuriously waking up this cpu */ 218 plat_arm_gic_cpuif_disable(); 219 220 /* 221 * The Redistributor is not powered off as it can potentially prevent 222 * wake up events reaching the CPUIF and/or might lead to losing 223 * register context. 224 */ 225 226 /* Perform the common cluster specific operations */ 227 if (target_state->pwr_domain_state[ARM_PWR_LVL1] == 228 ARM_LOCAL_STATE_OFF) 229 fvp_cluster_pwrdwn_common(); 230 231 /* Perform the common system specific operations */ 232 if (target_state->pwr_domain_state[ARM_PWR_LVL2] == 233 ARM_LOCAL_STATE_OFF) 234 arm_system_pwr_domain_save(); 235 236 /* Program the power controller to power off this cpu. */ 237 fvp_pwrc_write_ppoffr(read_mpidr_el1()); 238 } 239 240 /******************************************************************************* 241 * FVP handler called when a power domain has just been powered on after 242 * being turned off earlier. The target_state encodes the low power state that 243 * each level has woken up from. 244 ******************************************************************************/ 245 static void fvp_pwr_domain_on_finish(const psci_power_state_t *target_state) 246 { 247 fvp_power_domain_on_finish_common(target_state); 248 249 /* Enable the gic cpu interface */ 250 plat_arm_gic_pcpu_init(); 251 252 /* Program the gic per-cpu distributor or re-distributor interface */ 253 plat_arm_gic_cpuif_enable(); 254 } 255 256 /******************************************************************************* 257 * FVP handler called when a power domain has just been powered on after 258 * having been suspended earlier. The target_state encodes the low power state 259 * that each level has woken up from. 260 * TODO: At the moment we reuse the on finisher and reinitialize the secure 261 * context. Need to implement a separate suspend finisher. 262 ******************************************************************************/ 263 static void fvp_pwr_domain_suspend_finish(const psci_power_state_t *target_state) 264 { 265 /* 266 * Nothing to be done on waking up from retention from CPU level. 267 */ 268 if (target_state->pwr_domain_state[ARM_PWR_LVL0] == 269 ARM_LOCAL_STATE_RET) 270 return; 271 272 fvp_power_domain_on_finish_common(target_state); 273 274 /* Enable the gic cpu interface */ 275 plat_arm_gic_cpuif_enable(); 276 } 277 278 /******************************************************************************* 279 * FVP handlers to shutdown/reboot the system 280 ******************************************************************************/ 281 static void __dead2 fvp_system_off(void) 282 { 283 /* Write the System Configuration Control Register */ 284 mmio_write_32(V2M_SYSREGS_BASE + V2M_SYS_CFGCTRL, 285 V2M_CFGCTRL_START | 286 V2M_CFGCTRL_RW | 287 V2M_CFGCTRL_FUNC(V2M_FUNC_SHUTDOWN)); 288 wfi(); 289 ERROR("FVP System Off: operation not handled.\n"); 290 panic(); 291 } 292 293 static void __dead2 fvp_system_reset(void) 294 { 295 /* Write the System Configuration Control Register */ 296 mmio_write_32(V2M_SYSREGS_BASE + V2M_SYS_CFGCTRL, 297 V2M_CFGCTRL_START | 298 V2M_CFGCTRL_RW | 299 V2M_CFGCTRL_FUNC(V2M_FUNC_REBOOT)); 300 wfi(); 301 ERROR("FVP System Reset: operation not handled.\n"); 302 panic(); 303 } 304 305 static int fvp_node_hw_state(u_register_t target_cpu, 306 unsigned int power_level) 307 { 308 unsigned int psysr; 309 int ret; 310 311 /* 312 * The format of 'power_level' is implementation-defined, but 0 must 313 * mean a CPU. We also allow 1 to denote the cluster 314 */ 315 if ((power_level != ARM_PWR_LVL0) && (power_level != ARM_PWR_LVL1)) 316 return PSCI_E_INVALID_PARAMS; 317 318 /* 319 * Read the status of the given MPDIR from FVP power controller. The 320 * power controller only gives us on/off status, so map that to expected 321 * return values of the PSCI call 322 */ 323 psysr = fvp_pwrc_read_psysr(target_cpu); 324 if (psysr == PSYSR_INVALID) 325 return PSCI_E_INVALID_PARAMS; 326 327 if (power_level == ARM_PWR_LVL0) { 328 ret = ((psysr & PSYSR_AFF_L0) != 0U) ? HW_ON : HW_OFF; 329 } else { 330 /* power_level == ARM_PWR_LVL1 */ 331 ret = ((psysr & PSYSR_AFF_L1) != 0U) ? HW_ON : HW_OFF; 332 } 333 334 return ret; 335 } 336 337 /* 338 * The FVP doesn't truly support power management at SYSTEM power domain. The 339 * SYSTEM_SUSPEND will be down-graded to the cluster level within the platform 340 * layer. The `fake` SYSTEM_SUSPEND allows us to validate some of the driver 341 * save and restore sequences on FVP. 342 */ 343 #if !ARM_BL31_IN_DRAM 344 static void fvp_get_sys_suspend_power_state(psci_power_state_t *req_state) 345 { 346 unsigned int i; 347 348 for (i = ARM_PWR_LVL0; i <= PLAT_MAX_PWR_LVL; i++) 349 req_state->pwr_domain_state[i] = ARM_LOCAL_STATE_OFF; 350 } 351 #endif 352 353 /******************************************************************************* 354 * Handler to filter PSCI requests. 355 ******************************************************************************/ 356 /* 357 * The system power domain suspend is only supported only via 358 * PSCI SYSTEM_SUSPEND API. PSCI CPU_SUSPEND request to system power domain 359 * will be downgraded to the lower level. 360 */ 361 static int fvp_validate_power_state(unsigned int power_state, 362 psci_power_state_t *req_state) 363 { 364 int rc; 365 rc = arm_validate_power_state(power_state, req_state); 366 367 /* 368 * Ensure that the system power domain level is never suspended 369 * via PSCI CPU SUSPEND API. Currently system suspend is only 370 * supported via PSCI SYSTEM SUSPEND API. 371 */ 372 req_state->pwr_domain_state[ARM_PWR_LVL2] = ARM_LOCAL_STATE_RUN; 373 return rc; 374 } 375 376 /* 377 * Custom `translate_power_state_by_mpidr` handler for FVP. Unlike in the 378 * `fvp_validate_power_state`, we do not downgrade the system power 379 * domain level request in `power_state` as it will be used to query the 380 * PSCI_STAT_COUNT/RESIDENCY at the system power domain level. 381 */ 382 static int fvp_translate_power_state_by_mpidr(u_register_t mpidr, 383 unsigned int power_state, 384 psci_power_state_t *output_state) 385 { 386 return arm_validate_power_state(power_state, output_state); 387 } 388 389 /******************************************************************************* 390 * Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard 391 * platform layer will take care of registering the handlers with PSCI. 392 ******************************************************************************/ 393 plat_psci_ops_t plat_arm_psci_pm_ops = { 394 .cpu_standby = fvp_cpu_standby, 395 .pwr_domain_on = fvp_pwr_domain_on, 396 .pwr_domain_off = fvp_pwr_domain_off, 397 .pwr_domain_suspend = fvp_pwr_domain_suspend, 398 .pwr_domain_on_finish = fvp_pwr_domain_on_finish, 399 .pwr_domain_suspend_finish = fvp_pwr_domain_suspend_finish, 400 .system_off = fvp_system_off, 401 .system_reset = fvp_system_reset, 402 .validate_power_state = fvp_validate_power_state, 403 .validate_ns_entrypoint = arm_validate_psci_entrypoint, 404 .translate_power_state_by_mpidr = fvp_translate_power_state_by_mpidr, 405 .get_node_hw_state = fvp_node_hw_state, 406 #if !ARM_BL31_IN_DRAM 407 /* 408 * The TrustZone Controller is set up during the warmboot sequence after 409 * resuming the CPU from a SYSTEM_SUSPEND. If BL31 is located in SRAM 410 * this is not a problem but, if it is in TZC-secured DRAM, it tries to 411 * reconfigure the same memory it is running on, causing an exception. 412 */ 413 .get_sys_suspend_power_state = fvp_get_sys_suspend_power_state, 414 #endif 415 .mem_protect_chk = arm_psci_mem_protect_chk, 416 .read_mem_protect = arm_psci_read_mem_protect, 417 .write_mem_protect = arm_nor_psci_write_mem_protect, 418 }; 419