1*e2e90fa1SBoyan Karatotev /* 2*e2e90fa1SBoyan Karatotev * Copyright (c) 2025, Arm Limited and Contributors. All rights reserved. 3*e2e90fa1SBoyan Karatotev * 4*e2e90fa1SBoyan Karatotev * SPDX-License-Identifier: BSD-3-Clause 5*e2e90fa1SBoyan Karatotev */ 6*e2e90fa1SBoyan Karatotev 7*e2e90fa1SBoyan Karatotev #include <drivers/arm/gicv5.h> 8*e2e90fa1SBoyan Karatotev #include <platform_def.h> 9*e2e90fa1SBoyan Karatotev 10*e2e90fa1SBoyan Karatotev /* wire 26 is the timer interrupt. Will be assigned NS by default */ 11*e2e90fa1SBoyan Karatotev struct gicv5_wire_props irs0_spis[] = { 12*e2e90fa1SBoyan Karatotev }; 13*e2e90fa1SBoyan Karatotev 14*e2e90fa1SBoyan Karatotev struct gicv5_wire_props iwb0_wires[] = { 15*e2e90fa1SBoyan Karatotev }; 16*e2e90fa1SBoyan Karatotev 17*e2e90fa1SBoyan Karatotev struct gicv5_irs irss[] = {{ 18*e2e90fa1SBoyan Karatotev .el3_config_frame = BASE_IRS_BASE, 19*e2e90fa1SBoyan Karatotev .spis = irs0_spis, 20*e2e90fa1SBoyan Karatotev .num_spis = ARRAY_SIZE(irs0_spis), 21*e2e90fa1SBoyan Karatotev }}; 22*e2e90fa1SBoyan Karatotev 23*e2e90fa1SBoyan Karatotev struct gicv5_iwb iwbs[] = {{ 24*e2e90fa1SBoyan Karatotev .config_frame = BASE_IWB_BASE, 25*e2e90fa1SBoyan Karatotev .wires = iwb0_wires, 26*e2e90fa1SBoyan Karatotev .num_wires = ARRAY_SIZE(iwb0_wires) 27*e2e90fa1SBoyan Karatotev }}; 28*e2e90fa1SBoyan Karatotev 29*e2e90fa1SBoyan Karatotev const struct gicv5_driver_data plat_gicv5_driver_data = { 30*e2e90fa1SBoyan Karatotev .irss = irss, 31*e2e90fa1SBoyan Karatotev .iwbs = iwbs, 32*e2e90fa1SBoyan Karatotev .num_irss = ARRAY_SIZE(irss), 33*e2e90fa1SBoyan Karatotev .num_iwbs = ARRAY_SIZE(iwbs) 34*e2e90fa1SBoyan Karatotev }; 35*e2e90fa1SBoyan Karatotev fvp_gic_driver_pre_init(void)36*e2e90fa1SBoyan Karatotevvoid fvp_gic_driver_pre_init(void) 37*e2e90fa1SBoyan Karatotev { 38*e2e90fa1SBoyan Karatotev } 39*e2e90fa1SBoyan Karatotev fvp_pcpu_init(void)40*e2e90fa1SBoyan Karatotevvoid fvp_pcpu_init(void) 41*e2e90fa1SBoyan Karatotev { 42*e2e90fa1SBoyan Karatotev } 43