1 /* 2 * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <platform_def.h> 9 10 #include <common/debug.h> 11 #include <common/interrupt_props.h> 12 #include <drivers/arm/gicv3.h> 13 #include <fconf_hw_config_getter.h> 14 #include <lib/utils.h> 15 #include <plat/arm/common/plat_arm.h> 16 #include <plat/arm/common/fconf_sec_intr_config.h> 17 #include <plat/common/platform.h> 18 19 #if FVP_GICR_REGION_PROTECTION 20 /* To indicate GICR region of the core initialized as Read-Write */ 21 static bool fvp_gicr_rw_region_init[PLATFORM_CORE_COUNT] = {false}; 22 #endif /* FVP_GICR_REGION_PROTECTION */ 23 24 /* The GICv3 driver only needs to be initialized in EL3 */ 25 static uintptr_t fvp_rdistif_base_addrs[PLATFORM_CORE_COUNT]; 26 27 /* Default GICR base address to be used for GICR probe. */ 28 static uint64_t fvp_gicr_base_addrs[2] = { 0U }; 29 30 /* List of zero terminated GICR frame addresses which CPUs will probe */ 31 static uint64_t *fvp_gicr_frames = fvp_gicr_base_addrs; 32 33 #if !(SEC_INT_DESC_IN_FCONF && ((!defined(__aarch64__) && defined(IMAGE_BL32)) || \ 34 (defined(__aarch64__) && defined(IMAGE_BL31)))) 35 static const interrupt_prop_t fvp_interrupt_props[] = { 36 PLAT_ARM_G1S_IRQ_PROPS(INTR_GROUP1S), 37 PLAT_ARM_G0_IRQ_PROPS(INTR_GROUP0) 38 }; 39 #endif 40 41 /* 42 * MPIDR hashing function for translating MPIDRs read from GICR_TYPER register 43 * to core position. 44 * 45 * Calculating core position is dependent on MPIDR_EL1.MT bit. However, affinity 46 * values read from GICR_TYPER don't have an MT field. To reuse the same 47 * translation used for CPUs, we insert MT bit read from the PE's MPIDR into 48 * that read from GICR_TYPER. 49 * 50 * Assumptions: 51 * 52 * - All CPUs implemented in the system have MPIDR_EL1.MT bit set; 53 * - No CPUs implemented in the system use affinity level 3. 54 */ 55 static unsigned int fvp_gicv3_mpidr_hash(u_register_t mpidr) 56 { 57 u_register_t temp_mpidr = mpidr; 58 59 temp_mpidr |= (read_mpidr_el1() & MPIDR_MT_MASK); 60 return plat_arm_calc_core_pos(temp_mpidr); 61 } 62 63 64 static gicv3_driver_data_t fvp_gic_data = { 65 .rdistif_num = PLATFORM_CORE_COUNT, 66 .rdistif_base_addrs = fvp_rdistif_base_addrs, 67 .mpidr_to_core_pos = fvp_gicv3_mpidr_hash 68 }; 69 70 /****************************************************************************** 71 * This function gets called per core to make its redistributor frame rw 72 *****************************************************************************/ 73 static void fvp_gicv3_make_rdistrif_rw(void) 74 { 75 #if FVP_GICR_REGION_PROTECTION 76 unsigned int core_pos = plat_my_core_pos(); 77 78 /* Make the redistributor frame RW if it is not done previously */ 79 if (fvp_gicr_rw_region_init[core_pos] != true) { 80 int ret = xlat_change_mem_attributes(BASE_GICR_BASE + 81 (core_pos * BASE_GICR_SIZE), 82 BASE_GICR_SIZE, 83 MT_EXECUTE_NEVER | 84 MT_DEVICE | MT_RW | 85 MT_SECURE); 86 87 if (ret != 0) { 88 ERROR("Failed to make redistributor frame \ 89 read write = %d\n", ret); 90 panic(); 91 } else { 92 fvp_gicr_rw_region_init[core_pos] = true; 93 } 94 } 95 #else 96 return; 97 #endif /* FVP_GICR_REGION_PROTECTION */ 98 } 99 100 void plat_arm_gic_driver_init(void) 101 { 102 fvp_gicv3_make_rdistrif_rw(); 103 /* 104 * Get GICD and GICR base addressed through FCONF APIs. 105 * FCONF is not supported in BL32 for FVP. 106 */ 107 #if (!defined(__aarch64__) && defined(IMAGE_BL32)) || \ 108 (defined(__aarch64__) && defined(IMAGE_BL31)) 109 fvp_gic_data.gicd_base = (uintptr_t)FCONF_GET_PROPERTY(hw_config, 110 gicv3_config, 111 gicd_base); 112 fvp_gicr_base_addrs[0] = FCONF_GET_PROPERTY(hw_config, gicv3_config, 113 gicr_base); 114 #if SEC_INT_DESC_IN_FCONF 115 fvp_gic_data.interrupt_props = FCONF_GET_PROPERTY(hw_config, 116 sec_intr_prop, descriptor); 117 fvp_gic_data.interrupt_props_num = FCONF_GET_PROPERTY(hw_config, 118 sec_intr_prop, count); 119 #else 120 fvp_gic_data.interrupt_props = fvp_interrupt_props; 121 fvp_gic_data.interrupt_props_num = ARRAY_SIZE(fvp_interrupt_props); 122 #endif 123 #else 124 fvp_gic_data.gicd_base = PLAT_ARM_GICD_BASE; 125 fvp_gicr_base_addrs[0] = PLAT_ARM_GICR_BASE; 126 fvp_gic_data.interrupt_props = fvp_interrupt_props; 127 fvp_gic_data.interrupt_props_num = ARRAY_SIZE(fvp_interrupt_props); 128 #endif 129 130 /* 131 * The GICv3 driver is initialized in EL3 and does not need 132 * to be initialized again in SEL1. This is because the S-EL1 133 * can use GIC system registers to manage interrupts and does 134 * not need GIC interface base addresses to be configured. 135 */ 136 137 #if (!defined(__aarch64__) && defined(IMAGE_BL32)) || \ 138 (defined(__aarch64__) && defined(IMAGE_BL31)) 139 gicv3_driver_init(&fvp_gic_data); 140 if (gicv3_rdistif_probe((uintptr_t)fvp_gicr_base_addrs[0]) == -1) { 141 ERROR("No GICR base frame found for Primary CPU\n"); 142 panic(); 143 } 144 #endif 145 } 146 147 /****************************************************************************** 148 * Function to iterate over all GICR frames and discover the corresponding 149 * per-cpu redistributor frame as well as initialize the corresponding 150 * interface in GICv3. 151 *****************************************************************************/ 152 void plat_arm_gic_pcpu_init(void) 153 { 154 int result; 155 const uint64_t *plat_gicr_frames = fvp_gicr_frames; 156 157 fvp_gicv3_make_rdistrif_rw(); 158 159 do { 160 result = gicv3_rdistif_probe(*plat_gicr_frames); 161 162 /* If the probe is successful, no need to proceed further */ 163 if (result == 0) 164 break; 165 166 plat_gicr_frames++; 167 } while (*plat_gicr_frames != 0U); 168 169 if (result == -1) { 170 ERROR("No GICR base frame found for CPU 0x%lx\n", read_mpidr()); 171 panic(); 172 } 173 gicv3_rdistif_init(plat_my_core_pos()); 174 } 175