1 /* 2 * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <platform_def.h> 9 10 #include <common/interrupt_props.h> 11 #include <drivers/arm/gicv3.h> 12 #include <fconf_hw_config_getter.h> 13 #include <lib/utils.h> 14 #include <plat/arm/common/plat_arm.h> 15 #include <plat/common/platform.h> 16 17 /* The GICv3 driver only needs to be initialized in EL3 */ 18 static uintptr_t fvp_rdistif_base_addrs[PLATFORM_CORE_COUNT]; 19 20 /* Default GICR base address to be used for GICR probe. */ 21 static uint64_t fvp_gicr_base_addrs[2] = { 0U }; 22 23 /* List of zero terminated GICR frame addresses which CPUs will probe */ 24 static uint64_t *fvp_gicr_frames = fvp_gicr_base_addrs; 25 26 static const interrupt_prop_t fvp_interrupt_props[] = { 27 PLAT_ARM_G1S_IRQ_PROPS(INTR_GROUP1S), 28 PLAT_ARM_G0_IRQ_PROPS(INTR_GROUP0) 29 }; 30 31 /* 32 * MPIDR hashing function for translating MPIDRs read from GICR_TYPER register 33 * to core position. 34 * 35 * Calculating core position is dependent on MPIDR_EL1.MT bit. However, affinity 36 * values read from GICR_TYPER don't have an MT field. To reuse the same 37 * translation used for CPUs, we insert MT bit read from the PE's MPIDR into 38 * that read from GICR_TYPER. 39 * 40 * Assumptions: 41 * 42 * - All CPUs implemented in the system have MPIDR_EL1.MT bit set; 43 * - No CPUs implemented in the system use affinity level 3. 44 */ 45 static unsigned int fvp_gicv3_mpidr_hash(u_register_t mpidr) 46 { 47 u_register_t temp_mpidr = mpidr; 48 49 temp_mpidr |= (read_mpidr_el1() & MPIDR_MT_MASK); 50 return plat_arm_calc_core_pos(temp_mpidr); 51 } 52 53 54 static gicv3_driver_data_t fvp_gic_data = { 55 .interrupt_props = fvp_interrupt_props, 56 .interrupt_props_num = ARRAY_SIZE(fvp_interrupt_props), 57 .rdistif_num = PLATFORM_CORE_COUNT, 58 .rdistif_base_addrs = fvp_rdistif_base_addrs, 59 .mpidr_to_core_pos = fvp_gicv3_mpidr_hash 60 }; 61 62 void plat_arm_gic_driver_init(void) 63 { 64 /* Get GICD and GICR base addressed through FCONF APIs */ 65 #if (!defined(__aarch64__) && defined(IMAGE_BL32)) || \ 66 (defined(__aarch64__) && defined(IMAGE_BL31)) 67 fvp_gic_data.gicd_base = (uintptr_t)FCONF_GET_PROPERTY(hw_config, 68 gicv3_config, 69 gicd_base); 70 fvp_gicr_base_addrs[0] = FCONF_GET_PROPERTY(hw_config, gicv3_config, 71 gicr_base); 72 #else 73 fvp_gic_data.gicd_base = PLAT_ARM_GICD_BASE; 74 fvp_gicr_base_addrs[0] = PLAT_ARM_GICR_BASE; 75 #endif 76 77 /* 78 * The GICv3 driver is initialized in EL3 and does not need 79 * to be initialized again in SEL1. This is because the S-EL1 80 * can use GIC system registers to manage interrupts and does 81 * not need GIC interface base addresses to be configured. 82 */ 83 84 #if (!defined(__aarch64__) && defined(IMAGE_BL32)) || \ 85 (defined(__aarch64__) && defined(IMAGE_BL31)) 86 gicv3_driver_init(&fvp_gic_data); 87 if (gicv3_rdistif_probe((uintptr_t)fvp_gicr_base_addrs[0]) == -1) { 88 ERROR("No GICR base frame found for Primary CPU\n"); 89 panic(); 90 } 91 #endif 92 } 93 94 /****************************************************************************** 95 * Function to iterate over all GICR frames and discover the corresponding 96 * per-cpu redistributor frame as well as initialize the corresponding 97 * interface in GICv3. 98 *****************************************************************************/ 99 void plat_arm_gic_pcpu_init(void) 100 { 101 int result; 102 const uint64_t *plat_gicr_frames = fvp_gicr_frames; 103 104 do { 105 result = gicv3_rdistif_probe(*plat_gicr_frames); 106 107 /* If the probe is successful, no need to proceed further */ 108 if (result == 0) 109 break; 110 111 plat_gicr_frames++; 112 } while (*plat_gicr_frames != 0U); 113 114 if (result == -1) { 115 ERROR("No GICR base frame found for CPU 0x%lx\n", read_mpidr()); 116 panic(); 117 } 118 gicv3_rdistif_init(plat_my_core_pos()); 119 } 120