1 /* 2 * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <platform_def.h> 9 10 #include <common/interrupt_props.h> 11 #include <drivers/arm/gicv3.h> 12 #include <fconf_hw_config_getter.h> 13 #include <lib/utils.h> 14 #include <plat/arm/common/plat_arm.h> 15 #include <plat/arm/common/fconf_sec_intr_config.h> 16 #include <plat/common/platform.h> 17 18 /* The GICv3 driver only needs to be initialized in EL3 */ 19 static uintptr_t fvp_rdistif_base_addrs[PLATFORM_CORE_COUNT]; 20 21 /* Default GICR base address to be used for GICR probe. */ 22 static uint64_t fvp_gicr_base_addrs[2] = { 0U }; 23 24 /* List of zero terminated GICR frame addresses which CPUs will probe */ 25 static uint64_t *fvp_gicr_frames = fvp_gicr_base_addrs; 26 27 #if !(SEC_INT_DESC_IN_FCONF && ((!defined(__aarch64__) && defined(IMAGE_BL32)) || \ 28 (defined(__aarch64__) && defined(IMAGE_BL31)))) 29 static const interrupt_prop_t fvp_interrupt_props[] = { 30 PLAT_ARM_G1S_IRQ_PROPS(INTR_GROUP1S), 31 PLAT_ARM_G0_IRQ_PROPS(INTR_GROUP0) 32 }; 33 #endif 34 35 /* 36 * MPIDR hashing function for translating MPIDRs read from GICR_TYPER register 37 * to core position. 38 * 39 * Calculating core position is dependent on MPIDR_EL1.MT bit. However, affinity 40 * values read from GICR_TYPER don't have an MT field. To reuse the same 41 * translation used for CPUs, we insert MT bit read from the PE's MPIDR into 42 * that read from GICR_TYPER. 43 * 44 * Assumptions: 45 * 46 * - All CPUs implemented in the system have MPIDR_EL1.MT bit set; 47 * - No CPUs implemented in the system use affinity level 3. 48 */ 49 static unsigned int fvp_gicv3_mpidr_hash(u_register_t mpidr) 50 { 51 u_register_t temp_mpidr = mpidr; 52 53 temp_mpidr |= (read_mpidr_el1() & MPIDR_MT_MASK); 54 return plat_arm_calc_core_pos(temp_mpidr); 55 } 56 57 58 static gicv3_driver_data_t fvp_gic_data = { 59 .rdistif_num = PLATFORM_CORE_COUNT, 60 .rdistif_base_addrs = fvp_rdistif_base_addrs, 61 .mpidr_to_core_pos = fvp_gicv3_mpidr_hash 62 }; 63 64 void plat_arm_gic_driver_init(void) 65 { 66 /* 67 * Get GICD and GICR base addressed through FCONF APIs. 68 * FCONF is not supported in BL32 for FVP. 69 */ 70 #if (!defined(__aarch64__) && defined(IMAGE_BL32)) || \ 71 (defined(__aarch64__) && defined(IMAGE_BL31)) 72 fvp_gic_data.gicd_base = (uintptr_t)FCONF_GET_PROPERTY(hw_config, 73 gicv3_config, 74 gicd_base); 75 fvp_gicr_base_addrs[0] = FCONF_GET_PROPERTY(hw_config, gicv3_config, 76 gicr_base); 77 #if SEC_INT_DESC_IN_FCONF 78 fvp_gic_data.interrupt_props = FCONF_GET_PROPERTY(hw_config, 79 sec_intr_prop, descriptor); 80 fvp_gic_data.interrupt_props_num = FCONF_GET_PROPERTY(hw_config, 81 sec_intr_prop, count); 82 #else 83 fvp_gic_data.interrupt_props = fvp_interrupt_props; 84 fvp_gic_data.interrupt_props_num = ARRAY_SIZE(fvp_interrupt_props); 85 #endif 86 #else 87 fvp_gic_data.gicd_base = PLAT_ARM_GICD_BASE; 88 fvp_gicr_base_addrs[0] = PLAT_ARM_GICR_BASE; 89 fvp_gic_data.interrupt_props = fvp_interrupt_props; 90 fvp_gic_data.interrupt_props_num = ARRAY_SIZE(fvp_interrupt_props); 91 #endif 92 93 /* 94 * The GICv3 driver is initialized in EL3 and does not need 95 * to be initialized again in SEL1. This is because the S-EL1 96 * can use GIC system registers to manage interrupts and does 97 * not need GIC interface base addresses to be configured. 98 */ 99 100 #if (!defined(__aarch64__) && defined(IMAGE_BL32)) || \ 101 (defined(__aarch64__) && defined(IMAGE_BL31)) 102 gicv3_driver_init(&fvp_gic_data); 103 if (gicv3_rdistif_probe((uintptr_t)fvp_gicr_base_addrs[0]) == -1) { 104 ERROR("No GICR base frame found for Primary CPU\n"); 105 panic(); 106 } 107 #endif 108 } 109 110 /****************************************************************************** 111 * Function to iterate over all GICR frames and discover the corresponding 112 * per-cpu redistributor frame as well as initialize the corresponding 113 * interface in GICv3. 114 *****************************************************************************/ 115 void plat_arm_gic_pcpu_init(void) 116 { 117 int result; 118 const uint64_t *plat_gicr_frames = fvp_gicr_frames; 119 120 do { 121 result = gicv3_rdistif_probe(*plat_gicr_frames); 122 123 /* If the probe is successful, no need to proceed further */ 124 if (result == 0) 125 break; 126 127 plat_gicr_frames++; 128 } while (*plat_gicr_frames != 0U); 129 130 if (result == -1) { 131 ERROR("No GICR base frame found for CPU 0x%lx\n", read_mpidr()); 132 panic(); 133 } 134 gicv3_rdistif_init(plat_my_core_pos()); 135 } 136