1 /* 2 * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __FVP_DEF_H__ 32 #define __FVP_DEF_H__ 33 34 #include <arm_def.h> 35 36 37 #define FVP_MAX_CPUS_PER_CLUSTER 4 38 39 #define FVP_PRIMARY_CPU 0x0 40 41 /******************************************************************************* 42 * FVP memory map related constants 43 ******************************************************************************/ 44 45 #define FLASH1_BASE 0x0c000000 46 #define FLASH1_SIZE 0x04000000 47 48 #define PSRAM_BASE 0x14000000 49 #define PSRAM_SIZE 0x04000000 50 51 #define VRAM_BASE 0x18000000 52 #define VRAM_SIZE 0x02000000 53 54 /* Aggregate of all devices in the first GB */ 55 #define DEVICE0_BASE 0x20000000 56 #define DEVICE0_SIZE 0x0c200000 57 58 #define DEVICE1_BASE 0x2f000000 59 #define DEVICE1_SIZE 0x200000 60 61 /* Devices in the second GB */ 62 #define DEVICE2_BASE 0x7fe00000 63 #define DEVICE2_SIZE 0x00200000 64 65 #define NSRAM_BASE 0x2e000000 66 #define NSRAM_SIZE 0x10000 67 68 #define PCIE_EXP_BASE 0x40000000 69 #define TZRNG_BASE 0x7fe60000 70 #define TZNVCTR_BASE 0x7fe70000 71 72 /* Keys */ 73 #define SOC_KEYS_BASE 0x7fe80000 74 #define TZ_PUB_KEY_HASH_BASE (SOC_KEYS_BASE + 0x0000) 75 #define TZ_PUB_KEY_HASH_SIZE 32 76 #define HU_KEY_BASE (SOC_KEYS_BASE + 0x0020) 77 #define HU_KEY_SIZE 16 78 #define END_KEY_BASE (SOC_KEYS_BASE + 0x0044) 79 #define END_KEY_SIZE 32 80 81 /* Constants to distinguish FVP type */ 82 #define HBI_BASE_FVP 0x020 83 #define REV_BASE_FVP_V0 0x0 84 85 #define HBI_FOUNDATION_FVP 0x010 86 #define REV_FOUNDATION_FVP_V2_0 0x0 87 #define REV_FOUNDATION_FVP_V2_1 0x1 88 #define REV_FOUNDATION_FVP_v9_1 0x2 89 90 #define BLD_GIC_VE_MMAP 0x0 91 #define BLD_GIC_A53A57_MMAP 0x1 92 93 #define ARCH_MODEL 0x1 94 95 /* FVP Power controller base address*/ 96 #define PWRC_BASE 0x1c100000 97 98 /* FVP SP804 timer frequency is 35 MHz*/ 99 #define SP804_TIMER_CLKMULT 35 100 #define SP804_TIMER_CLKDIV 1 101 102 /******************************************************************************* 103 * GIC-400 & interrupt handling related constants 104 ******************************************************************************/ 105 /* VE compatible GIC memory map */ 106 #define VE_GICD_BASE 0x2c001000 107 #define VE_GICC_BASE 0x2c002000 108 #define VE_GICH_BASE 0x2c004000 109 #define VE_GICV_BASE 0x2c006000 110 111 /* Base FVP compatible GIC memory map */ 112 #define BASE_GICD_BASE 0x2f000000 113 #define BASE_GICR_BASE 0x2f100000 114 #define BASE_GICC_BASE 0x2c000000 115 #define BASE_GICH_BASE 0x2c010000 116 #define BASE_GICV_BASE 0x2c02f000 117 118 #define FVP_IRQ_TZ_WDOG 56 119 #define FVP_IRQ_SEC_SYS_TIMER 57 120 121 122 /******************************************************************************* 123 * TrustZone address space controller related constants 124 ******************************************************************************/ 125 126 /* NSAIDs used by devices in TZC filter 0 on FVP */ 127 #define FVP_NSAID_DEFAULT 0 128 #define FVP_NSAID_PCI 1 129 #define FVP_NSAID_VIRTIO 8 /* from FVP v5.6 onwards */ 130 #define FVP_NSAID_AP 9 /* Application Processors */ 131 #define FVP_NSAID_VIRTIO_OLD 15 /* until FVP v5.5 */ 132 133 /* NSAIDs used by devices in TZC filter 2 on FVP */ 134 #define FVP_NSAID_HDLCD0 2 135 #define FVP_NSAID_CLCD 7 136 137 /******************************************************************************* 138 * Shared Data 139 ******************************************************************************/ 140 141 /* Entrypoint mailboxes */ 142 #define MBOX_BASE ARM_SHARED_RAM_BASE 143 144 145 #endif /* __FVP_DEF_H__ */ 146