1 /* 2 * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __FVP_DEF_H__ 8 #define __FVP_DEF_H__ 9 10 #ifndef FVP_CLUSTER_COUNT 11 #define FVP_CLUSTER_COUNT 2 12 #endif 13 #define FVP_MAX_CPUS_PER_CLUSTER 4 14 15 #define FVP_PRIMARY_CPU 0x0 16 17 /* Defines for the Interconnect build selection */ 18 #define FVP_CCI 1 19 #define FVP_CCN 2 20 21 /******************************************************************************* 22 * FVP memory map related constants 23 ******************************************************************************/ 24 25 #define FLASH1_BASE 0x0c000000 26 #define FLASH1_SIZE 0x04000000 27 28 #define PSRAM_BASE 0x14000000 29 #define PSRAM_SIZE 0x04000000 30 31 #define VRAM_BASE 0x18000000 32 #define VRAM_SIZE 0x02000000 33 34 /* Aggregate of all devices in the first GB */ 35 #define DEVICE0_BASE 0x20000000 36 #define DEVICE0_SIZE 0x0c200000 37 38 /* 39 * In case of FVP models with CCN, the CCN register space overlaps into 40 * the NSRAM area. 41 */ 42 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 43 #define DEVICE1_BASE 0x2e000000 44 #define DEVICE1_SIZE 0x1A00000 45 #else 46 #define DEVICE1_BASE 0x2f000000 47 #define DEVICE1_SIZE 0x200000 48 #define NSRAM_BASE 0x2e000000 49 #define NSRAM_SIZE 0x10000 50 #endif 51 /* Devices in the second GB */ 52 #define DEVICE2_BASE 0x7fe00000 53 #define DEVICE2_SIZE 0x00200000 54 55 #define PCIE_EXP_BASE 0x40000000 56 #define TZRNG_BASE 0x7fe60000 57 58 /* Non-volatile counters */ 59 #define TRUSTED_NVCTR_BASE 0x7fe70000 60 #define TFW_NVCTR_BASE (TRUSTED_NVCTR_BASE + 0x0000) 61 #define TFW_NVCTR_SIZE 4 62 #define NTFW_CTR_BASE (TRUSTED_NVCTR_BASE + 0x0004) 63 #define NTFW_CTR_SIZE 4 64 65 /* Keys */ 66 #define SOC_KEYS_BASE 0x7fe80000 67 #define TZ_PUB_KEY_HASH_BASE (SOC_KEYS_BASE + 0x0000) 68 #define TZ_PUB_KEY_HASH_SIZE 32 69 #define HU_KEY_BASE (SOC_KEYS_BASE + 0x0020) 70 #define HU_KEY_SIZE 16 71 #define END_KEY_BASE (SOC_KEYS_BASE + 0x0044) 72 #define END_KEY_SIZE 32 73 74 /* Constants to distinguish FVP type */ 75 #define HBI_BASE_FVP 0x020 76 #define REV_BASE_FVP_V0 0x0 77 78 #define HBI_FOUNDATION_FVP 0x010 79 #define REV_FOUNDATION_FVP_V2_0 0x0 80 #define REV_FOUNDATION_FVP_V2_1 0x1 81 #define REV_FOUNDATION_FVP_v9_1 0x2 82 #define REV_FOUNDATION_FVP_v9_6 0x3 83 84 #define BLD_GIC_VE_MMAP 0x0 85 #define BLD_GIC_A53A57_MMAP 0x1 86 87 #define ARCH_MODEL 0x1 88 89 /* FVP Power controller base address*/ 90 #define PWRC_BASE 0x1c100000 91 92 /* FVP SP804 timer frequency is 35 MHz*/ 93 #define SP804_TIMER_CLKMULT 1 94 #define SP804_TIMER_CLKDIV 35 95 96 /* SP810 controller. FVP specific flags */ 97 #define FVP_SP810_CTRL_TIM0_OV (1 << 16) 98 #define FVP_SP810_CTRL_TIM1_OV (1 << 18) 99 #define FVP_SP810_CTRL_TIM2_OV (1 << 20) 100 #define FVP_SP810_CTRL_TIM3_OV (1 << 22) 101 102 /******************************************************************************* 103 * GIC-400 & interrupt handling related constants 104 ******************************************************************************/ 105 /* VE compatible GIC memory map */ 106 #define VE_GICD_BASE 0x2c001000 107 #define VE_GICC_BASE 0x2c002000 108 #define VE_GICH_BASE 0x2c004000 109 #define VE_GICV_BASE 0x2c006000 110 111 /* Base FVP compatible GIC memory map */ 112 #define BASE_GICD_BASE 0x2f000000 113 #define BASE_GICR_BASE 0x2f100000 114 #define BASE_GICC_BASE 0x2c000000 115 #define BASE_GICH_BASE 0x2c010000 116 #define BASE_GICV_BASE 0x2c02f000 117 118 #define FVP_IRQ_TZ_WDOG 56 119 #define FVP_IRQ_SEC_SYS_TIMER 57 120 121 122 /******************************************************************************* 123 * TrustZone address space controller related constants 124 ******************************************************************************/ 125 126 /* NSAIDs used by devices in TZC filter 0 on FVP */ 127 #define FVP_NSAID_DEFAULT 0 128 #define FVP_NSAID_PCI 1 129 #define FVP_NSAID_VIRTIO 8 /* from FVP v5.6 onwards */ 130 #define FVP_NSAID_AP 9 /* Application Processors */ 131 #define FVP_NSAID_VIRTIO_OLD 15 /* until FVP v5.5 */ 132 133 /* NSAIDs used by devices in TZC filter 2 on FVP */ 134 #define FVP_NSAID_HDLCD0 2 135 #define FVP_NSAID_CLCD 7 136 137 #endif /* __FVP_DEF_H__ */ 138