1 /* 2 * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef FVP_DEF_H 8 #define FVP_DEF_H 9 10 #include <lib/utils_def.h> 11 12 #ifndef FVP_CLUSTER_COUNT 13 #error "FVP_CLUSTER_COUNT is not set in makefile" 14 #endif 15 16 #ifndef FVP_MAX_CPUS_PER_CLUSTER 17 #error "FVP_MAX_CPUS_PER_CLUSTER is not set in makefile" 18 #endif 19 20 #ifndef FVP_MAX_PE_PER_CPU 21 #error "FVP_MAX_PE_PER_CPU is not set in makefile" 22 #endif 23 24 #define FVP_PRIMARY_CPU 0x0 25 26 /* Defines for the Interconnect build selection */ 27 #define FVP_CCI 1 28 #define FVP_CCN 2 29 30 /******************************************************************************* 31 * FVP memory map related constants 32 ******************************************************************************/ 33 34 #define FLASH1_BASE UL(0x0c000000) 35 #define FLASH1_SIZE UL(0x04000000) 36 37 #define PSRAM_BASE UL(0x14000000) 38 #define PSRAM_SIZE UL(0x04000000) 39 40 #define VRAM_BASE UL(0x18000000) 41 #define VRAM_SIZE UL(0x02000000) 42 43 /* Aggregate of all devices in the first GB */ 44 #define DEVICE0_BASE UL(0x20000000) 45 #define DEVICE0_SIZE UL(0x0c200000) 46 47 /* 48 * In case of FVP models with CCN, the CCN register space overlaps into 49 * the NSRAM area. 50 */ 51 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 52 #define DEVICE1_BASE UL(0x2e000000) 53 #define DEVICE1_SIZE UL(0x1A00000) 54 #else 55 /* GICv2 and GICv3 mapping: GICD + CORE_COUNT * 128KB */ 56 #define DEVICE1_BASE BASE_GICD_BASE 57 #define DEVICE1_SIZE ((BASE_GICR_BASE - BASE_GICD_BASE) + \ 58 (PLATFORM_CORE_COUNT * 0x20000)) 59 #define NSRAM_BASE UL(0x2e000000) 60 #define NSRAM_SIZE UL(0x10000) 61 #endif 62 /* Devices in the second GB */ 63 #define DEVICE2_BASE UL(0x7fe00000) 64 #define DEVICE2_SIZE UL(0x00200000) 65 66 #define PCIE_EXP_BASE UL(0x40000000) 67 #define TZRNG_BASE UL(0x7fe60000) 68 69 /* Non-volatile counters */ 70 #define TRUSTED_NVCTR_BASE UL(0x7fe70000) 71 #define TFW_NVCTR_BASE (TRUSTED_NVCTR_BASE + UL(0x0000)) 72 #define TFW_NVCTR_SIZE UL(4) 73 #define NTFW_CTR_BASE (TRUSTED_NVCTR_BASE + UL(0x0004)) 74 #define NTFW_CTR_SIZE UL(4) 75 76 /* Keys */ 77 #define SOC_KEYS_BASE UL(0x7fe80000) 78 #define TZ_PUB_KEY_HASH_BASE (SOC_KEYS_BASE + UL(0x0000)) 79 #define TZ_PUB_KEY_HASH_SIZE UL(32) 80 #define HU_KEY_BASE (SOC_KEYS_BASE + UL(0x0020)) 81 #define HU_KEY_SIZE UL(16) 82 #define END_KEY_BASE (SOC_KEYS_BASE + UL(0x0044)) 83 #define END_KEY_SIZE UL(32) 84 85 /* Constants to distinguish FVP type */ 86 #define HBI_BASE_FVP U(0x020) 87 #define REV_BASE_FVP_V0 U(0x0) 88 #define REV_BASE_FVP_REVC U(0x2) 89 90 #define HBI_FOUNDATION_FVP U(0x010) 91 #define REV_FOUNDATION_FVP_V2_0 U(0x0) 92 #define REV_FOUNDATION_FVP_V2_1 U(0x1) 93 #define REV_FOUNDATION_FVP_v9_1 U(0x2) 94 #define REV_FOUNDATION_FVP_v9_6 U(0x3) 95 96 #define BLD_GIC_VE_MMAP U(0x0) 97 #define BLD_GIC_A53A57_MMAP U(0x1) 98 99 #define ARCH_MODEL U(0x1) 100 101 /* FVP Power controller base address*/ 102 #define PWRC_BASE UL(0x1c100000) 103 104 /* FVP SP804 timer frequency is 35 MHz*/ 105 #define SP804_TIMER_CLKMULT 1 106 #define SP804_TIMER_CLKDIV 35 107 108 /* SP810 controller. FVP specific flags */ 109 #define FVP_SP810_CTRL_TIM0_OV BIT_32(16) 110 #define FVP_SP810_CTRL_TIM1_OV BIT_32(18) 111 #define FVP_SP810_CTRL_TIM2_OV BIT_32(20) 112 #define FVP_SP810_CTRL_TIM3_OV BIT_32(22) 113 114 /******************************************************************************* 115 * GIC & interrupt handling related constants 116 ******************************************************************************/ 117 /* VE compatible GIC memory map */ 118 #define VE_GICD_BASE UL(0x2c001000) 119 #define VE_GICC_BASE UL(0x2c002000) 120 #define VE_GICH_BASE UL(0x2c004000) 121 #define VE_GICV_BASE UL(0x2c006000) 122 123 /* Base FVP compatible GIC memory map */ 124 #define BASE_GICD_BASE UL(0x2f000000) 125 #define BASE_GICR_BASE UL(0x2f100000) 126 #define BASE_GICC_BASE UL(0x2c000000) 127 #define BASE_GICH_BASE UL(0x2c010000) 128 #define BASE_GICV_BASE UL(0x2c02f000) 129 130 #define FVP_IRQ_TZ_WDOG 56 131 #define FVP_IRQ_SEC_SYS_TIMER 57 132 133 /******************************************************************************* 134 * TrustZone address space controller related constants 135 ******************************************************************************/ 136 137 /* NSAIDs used by devices in TZC filter 0 on FVP */ 138 #define FVP_NSAID_DEFAULT 0 139 #define FVP_NSAID_PCI 1 140 #define FVP_NSAID_VIRTIO 8 /* from FVP v5.6 onwards */ 141 #define FVP_NSAID_AP 9 /* Application Processors */ 142 #define FVP_NSAID_VIRTIO_OLD 15 /* until FVP v5.5 */ 143 144 /* NSAIDs used by devices in TZC filter 2 on FVP */ 145 #define FVP_NSAID_HDLCD0 2 146 #define FVP_NSAID_CLCD 7 147 148 /******************************************************************************* 149 * Memprotect definitions 150 ******************************************************************************/ 151 /* PSCI memory protect definitions: 152 * This variable is stored in a non-secure flash because some ARM reference 153 * platforms do not have secure NVRAM. Real systems that provided MEM_PROTECT 154 * support must use a secure NVRAM to store the PSCI MEM_PROTECT definitions. 155 */ 156 #define PLAT_ARM_MEM_PROT_ADDR (V2M_FLASH0_BASE + \ 157 V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 158 159 #endif /* FVP_DEF_H */ 160