1 /* 2 * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __FVP_DEF_H__ 32 #define __FVP_DEF_H__ 33 34 #include <arm_def.h> 35 36 #ifndef FVP_CLUSTER_COUNT 37 #define FVP_CLUSTER_COUNT 2 38 #endif 39 #define FVP_MAX_CPUS_PER_CLUSTER 4 40 41 #define FVP_PRIMARY_CPU 0x0 42 43 /******************************************************************************* 44 * FVP memory map related constants 45 ******************************************************************************/ 46 47 #define FLASH1_BASE 0x0c000000 48 #define FLASH1_SIZE 0x04000000 49 50 #define PSRAM_BASE 0x14000000 51 #define PSRAM_SIZE 0x04000000 52 53 #define VRAM_BASE 0x18000000 54 #define VRAM_SIZE 0x02000000 55 56 /* Aggregate of all devices in the first GB */ 57 #define DEVICE0_BASE 0x20000000 58 #define DEVICE0_SIZE 0x0c200000 59 60 #define DEVICE1_BASE 0x2f000000 61 #define DEVICE1_SIZE 0x200000 62 63 /* Devices in the second GB */ 64 #define DEVICE2_BASE 0x7fe00000 65 #define DEVICE2_SIZE 0x00200000 66 67 #define NSRAM_BASE 0x2e000000 68 #define NSRAM_SIZE 0x10000 69 70 #define PCIE_EXP_BASE 0x40000000 71 #define TZRNG_BASE 0x7fe60000 72 #define TZNVCTR_BASE 0x7fe70000 73 74 /* Keys */ 75 #define SOC_KEYS_BASE 0x7fe80000 76 #define TZ_PUB_KEY_HASH_BASE (SOC_KEYS_BASE + 0x0000) 77 #define TZ_PUB_KEY_HASH_SIZE 32 78 #define HU_KEY_BASE (SOC_KEYS_BASE + 0x0020) 79 #define HU_KEY_SIZE 16 80 #define END_KEY_BASE (SOC_KEYS_BASE + 0x0044) 81 #define END_KEY_SIZE 32 82 83 /* Constants to distinguish FVP type */ 84 #define HBI_BASE_FVP 0x020 85 #define REV_BASE_FVP_V0 0x0 86 87 #define HBI_FOUNDATION_FVP 0x010 88 #define REV_FOUNDATION_FVP_V2_0 0x0 89 #define REV_FOUNDATION_FVP_V2_1 0x1 90 #define REV_FOUNDATION_FVP_v9_1 0x2 91 92 #define BLD_GIC_VE_MMAP 0x0 93 #define BLD_GIC_A53A57_MMAP 0x1 94 95 #define ARCH_MODEL 0x1 96 97 /* FVP Power controller base address*/ 98 #define PWRC_BASE 0x1c100000 99 100 /* FVP SP804 timer frequency is 35 MHz*/ 101 #define SP804_TIMER_CLKMULT 1 102 #define SP804_TIMER_CLKDIV 35 103 104 /* SP810 controller. FVP specific flags */ 105 #define FVP_SP810_CTRL_TIM0_OV (1 << 16) 106 #define FVP_SP810_CTRL_TIM1_OV (1 << 18) 107 #define FVP_SP810_CTRL_TIM2_OV (1 << 20) 108 #define FVP_SP810_CTRL_TIM3_OV (1 << 22) 109 110 /******************************************************************************* 111 * GIC-400 & interrupt handling related constants 112 ******************************************************************************/ 113 /* VE compatible GIC memory map */ 114 #define VE_GICD_BASE 0x2c001000 115 #define VE_GICC_BASE 0x2c002000 116 #define VE_GICH_BASE 0x2c004000 117 #define VE_GICV_BASE 0x2c006000 118 119 /* Base FVP compatible GIC memory map */ 120 #define BASE_GICD_BASE 0x2f000000 121 #define BASE_GICR_BASE 0x2f100000 122 #define BASE_GICC_BASE 0x2c000000 123 #define BASE_GICH_BASE 0x2c010000 124 #define BASE_GICV_BASE 0x2c02f000 125 126 #define FVP_IRQ_TZ_WDOG 56 127 #define FVP_IRQ_SEC_SYS_TIMER 57 128 129 130 /******************************************************************************* 131 * TrustZone address space controller related constants 132 ******************************************************************************/ 133 134 /* NSAIDs used by devices in TZC filter 0 on FVP */ 135 #define FVP_NSAID_DEFAULT 0 136 #define FVP_NSAID_PCI 1 137 #define FVP_NSAID_VIRTIO 8 /* from FVP v5.6 onwards */ 138 #define FVP_NSAID_AP 9 /* Application Processors */ 139 #define FVP_NSAID_VIRTIO_OLD 15 /* until FVP v5.5 */ 140 141 /* NSAIDs used by devices in TZC filter 2 on FVP */ 142 #define FVP_NSAID_HDLCD0 2 143 #define FVP_NSAID_CLCD 7 144 145 #endif /* __FVP_DEF_H__ */ 146