1 /* 2 * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __FVP_DEF_H__ 32 #define __FVP_DEF_H__ 33 34 #include <arm_def.h> 35 36 #ifndef FVP_CLUSTER_COUNT 37 #define FVP_CLUSTER_COUNT 2 38 #endif 39 #define FVP_MAX_CPUS_PER_CLUSTER 4 40 41 #define FVP_PRIMARY_CPU 0x0 42 43 /* Defines for the Interconnect build selection */ 44 #define FVP_CCI 1 45 #define FVP_CCN 2 46 47 /******************************************************************************* 48 * FVP memory map related constants 49 ******************************************************************************/ 50 51 #define FLASH1_BASE 0x0c000000 52 #define FLASH1_SIZE 0x04000000 53 54 #define PSRAM_BASE 0x14000000 55 #define PSRAM_SIZE 0x04000000 56 57 #define VRAM_BASE 0x18000000 58 #define VRAM_SIZE 0x02000000 59 60 /* Aggregate of all devices in the first GB */ 61 #define DEVICE0_BASE 0x20000000 62 #define DEVICE0_SIZE 0x0c200000 63 64 /* 65 * In case of FVP models with CCN, the CCN register space overlaps into 66 * the NSRAM area. 67 */ 68 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 69 #define DEVICE1_BASE 0x2e000000 70 #define DEVICE1_SIZE 0x1A00000 71 #else 72 #define DEVICE1_BASE 0x2f000000 73 #define DEVICE1_SIZE 0x200000 74 #define NSRAM_BASE 0x2e000000 75 #define NSRAM_SIZE 0x10000 76 #endif 77 /* Devices in the second GB */ 78 #define DEVICE2_BASE 0x7fe00000 79 #define DEVICE2_SIZE 0x00200000 80 81 #define PCIE_EXP_BASE 0x40000000 82 #define TZRNG_BASE 0x7fe60000 83 84 /* Non-volatile counters */ 85 #define TRUSTED_NVCTR_BASE 0x7fe70000 86 #define TFW_NVCTR_BASE (TRUSTED_NVCTR_BASE + 0x0000) 87 #define TFW_NVCTR_SIZE 4 88 #define NTFW_CTR_BASE (TRUSTED_NVCTR_BASE + 0x0004) 89 #define NTFW_CTR_SIZE 4 90 91 /* Keys */ 92 #define SOC_KEYS_BASE 0x7fe80000 93 #define TZ_PUB_KEY_HASH_BASE (SOC_KEYS_BASE + 0x0000) 94 #define TZ_PUB_KEY_HASH_SIZE 32 95 #define HU_KEY_BASE (SOC_KEYS_BASE + 0x0020) 96 #define HU_KEY_SIZE 16 97 #define END_KEY_BASE (SOC_KEYS_BASE + 0x0044) 98 #define END_KEY_SIZE 32 99 100 /* Constants to distinguish FVP type */ 101 #define HBI_BASE_FVP 0x020 102 #define REV_BASE_FVP_V0 0x0 103 104 #define HBI_FOUNDATION_FVP 0x010 105 #define REV_FOUNDATION_FVP_V2_0 0x0 106 #define REV_FOUNDATION_FVP_V2_1 0x1 107 #define REV_FOUNDATION_FVP_v9_1 0x2 108 #define REV_FOUNDATION_FVP_v9_6 0x3 109 110 #define BLD_GIC_VE_MMAP 0x0 111 #define BLD_GIC_A53A57_MMAP 0x1 112 113 #define ARCH_MODEL 0x1 114 115 /* FVP Power controller base address*/ 116 #define PWRC_BASE 0x1c100000 117 118 /* FVP SP804 timer frequency is 35 MHz*/ 119 #define SP804_TIMER_CLKMULT 1 120 #define SP804_TIMER_CLKDIV 35 121 122 /* SP810 controller. FVP specific flags */ 123 #define FVP_SP810_CTRL_TIM0_OV (1 << 16) 124 #define FVP_SP810_CTRL_TIM1_OV (1 << 18) 125 #define FVP_SP810_CTRL_TIM2_OV (1 << 20) 126 #define FVP_SP810_CTRL_TIM3_OV (1 << 22) 127 128 /******************************************************************************* 129 * GIC-400 & interrupt handling related constants 130 ******************************************************************************/ 131 /* VE compatible GIC memory map */ 132 #define VE_GICD_BASE 0x2c001000 133 #define VE_GICC_BASE 0x2c002000 134 #define VE_GICH_BASE 0x2c004000 135 #define VE_GICV_BASE 0x2c006000 136 137 /* Base FVP compatible GIC memory map */ 138 #define BASE_GICD_BASE 0x2f000000 139 #define BASE_GICR_BASE 0x2f100000 140 #define BASE_GICC_BASE 0x2c000000 141 #define BASE_GICH_BASE 0x2c010000 142 #define BASE_GICV_BASE 0x2c02f000 143 144 #define FVP_IRQ_TZ_WDOG 56 145 #define FVP_IRQ_SEC_SYS_TIMER 57 146 147 148 /******************************************************************************* 149 * TrustZone address space controller related constants 150 ******************************************************************************/ 151 152 /* NSAIDs used by devices in TZC filter 0 on FVP */ 153 #define FVP_NSAID_DEFAULT 0 154 #define FVP_NSAID_PCI 1 155 #define FVP_NSAID_VIRTIO 8 /* from FVP v5.6 onwards */ 156 #define FVP_NSAID_AP 9 /* Application Processors */ 157 #define FVP_NSAID_VIRTIO_OLD 15 /* until FVP v5.5 */ 158 159 /* NSAIDs used by devices in TZC filter 2 on FVP */ 160 #define FVP_NSAID_HDLCD0 2 161 #define FVP_NSAID_CLCD 7 162 163 #endif /* __FVP_DEF_H__ */ 164