xref: /rk3399_ARM-atf/plat/arm/board/fvp/fvp_cpu_errata.mk (revision c9f2634387b4ea29f61234c4fe0fc0515ad32f2b)
1d3bed158SSona Mathew#
2*c9f26343SSona Mathew# Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved.
3d3bed158SSona Mathew#
4d3bed158SSona Mathew# SPDX-License-Identifier: BSD-3-Clause
5d3bed158SSona Mathew#
6d3bed158SSona Mathew
7*c9f26343SSona Mathew# Flags to enable the cpu structures in the Errata ABI file
8*c9f26343SSona Mathew# file: services/std_svc/errata_abi/errata_abi_main.c. This is specifically
9*c9f26343SSona Mathew# for platforms that need to enable errata based on non-arm interconnect IP.
10d3bed158SSona Mathew
11d3bed158SSona Mathewifeq (${ERRATA_ABI_SUPPORT}, 1)
12d3bed158SSona Mathewifeq (${CTX_INCLUDE_AARCH32_REGS}, 0)
13d3bed158SSona MathewCORTEX_A78_H_INC	:= 1
147e030b37SArvind Ram PrakashNEOVERSE_N2_H_INC	:= 1
15d3bed158SSona MathewNEOVERSE_V1_H_INC	:= 1
16d3bed158SSona MathewCORTEX_A78_AE_H_INC	:= 1
17d3bed158SSona MathewCORTEX_A710_H_INC	:= 1
18d3bed158SSona MathewCORTEX_A715_H_INC 	:= 1
19d3bed158SSona MathewCORTEX_A78C_H_INC	:= 1
20d3bed158SSona MathewCORTEX_X2_H_INC		:= 1
21d3bed158SSona Mathew$(eval $(call add_define, CORTEX_A78_H_INC))
22d3bed158SSona Mathew$(eval $(call add_define, NEOVERSE_N1_H_INC))
237e030b37SArvind Ram Prakash$(eval $(call add_define, NEOVERSE_N2_H_INC))
24d3bed158SSona Mathew$(eval $(call add_define, NEOVERSE_V1_H_INC))
25d3bed158SSona Mathew$(eval $(call add_define, CORTEX_A78_AE_H_INC))
26d3bed158SSona Mathew$(eval $(call add_define, CORTEX_A710_H_INC))
27d3bed158SSona Mathew$(eval $(call add_define, CORTEX_A715_H_INC))
28d3bed158SSona Mathew$(eval $(call add_define, CORTEX_A78C_H_INC))
29d3bed158SSona Mathew$(eval $(call add_define, CORTEX_X2_H_INC))
30d3bed158SSona Mathewendif
31d3bed158SSona Mathewendif
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