xref: /rk3399_ARM-atf/plat/arm/board/fvp/fvp_cpu_errata.mk (revision 1ba369a5e0a982bf9ecccc71d17274763ea4e6a5)
1d3bed158SSona Mathew#
2c9f26343SSona Mathew# Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved.
3d3bed158SSona Mathew#
4d3bed158SSona Mathew# SPDX-License-Identifier: BSD-3-Clause
5d3bed158SSona Mathew#
6d3bed158SSona Mathew
7c9f26343SSona Mathew# Flags to enable the cpu structures in the Errata ABI file
8c9f26343SSona Mathew# file: services/std_svc/errata_abi/errata_abi_main.c. This is specifically
9c9f26343SSona Mathew# for platforms that need to enable errata based on non-arm interconnect IP.
10d3bed158SSona Mathew
11d3bed158SSona Mathewifeq (${ERRATA_ABI_SUPPORT}, 1)
12aceb9c9eSSona Mathewifeq (${ERRATA_NON_ARM_INTERCONNECT}, 1)
13d3bed158SSona Mathewifeq (${CTX_INCLUDE_AARCH32_REGS}, 0)
14*1ba369a5SSona MathewCORTEX_A710_H_INC	:= 1
15d3bed158SSona MathewCORTEX_A78_H_INC	:= 1
16*1ba369a5SSona MathewCORTEX_A78_AE_H_INC	:= 1
17*1ba369a5SSona MathewCORTEX_A78C_H_INC	:= 1
18*1ba369a5SSona MathewCORTEX_X3_H_INC		:= 1
197e030b37SArvind Ram PrakashNEOVERSE_N2_H_INC	:= 1
20d3bed158SSona MathewNEOVERSE_V1_H_INC	:= 1
21*1ba369a5SSona Mathew$(eval $(call add_define, CORTEX_A710_H_INC))
22d3bed158SSona Mathew$(eval $(call add_define, CORTEX_A78_H_INC))
23*1ba369a5SSona Mathew$(eval $(call add_define, CORTEX_A78_AE_H_INC))
24*1ba369a5SSona Mathew$(eval $(call add_define, CORTEX_A78C_H_INC))
25*1ba369a5SSona Mathew$(eval $(call add_define, CORTEX_X3_H_INC))
267e030b37SArvind Ram Prakash$(eval $(call add_define, NEOVERSE_N2_H_INC))
27d3bed158SSona Mathew$(eval $(call add_define, NEOVERSE_V1_H_INC))
28d3bed158SSona Mathewendif
29d3bed158SSona Mathewendif
30aceb9c9eSSona Mathewendif
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