1 /* 2 * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <common/debug.h> 10 #include <drivers/arm/cci.h> 11 #include <drivers/arm/ccn.h> 12 #include <drivers/arm/gicv2.h> 13 #include <lib/mmio.h> 14 #include <lib/xlat_tables/xlat_tables_compat.h> 15 #include <plat/common/platform.h> 16 #include <platform_def.h> 17 #include <services/secure_partition.h> 18 19 #include <arm_config.h> 20 #include <plat_arm.h> 21 22 #include "fvp_private.h" 23 24 /* Defines for GIC Driver build time selection */ 25 #define FVP_GICV2 1 26 #define FVP_GICV3 2 27 28 /******************************************************************************* 29 * arm_config holds the characteristics of the differences between the three FVP 30 * platforms (Base, A53_A57 & Foundation). It will be populated during cold boot 31 * at each boot stage by the primary before enabling the MMU (to allow 32 * interconnect configuration) & used thereafter. Each BL will have its own copy 33 * to allow independent operation. 34 ******************************************************************************/ 35 arm_config_t arm_config; 36 37 #define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \ 38 DEVICE0_SIZE, \ 39 MT_DEVICE | MT_RW | MT_SECURE) 40 41 #define MAP_DEVICE1 MAP_REGION_FLAT(DEVICE1_BASE, \ 42 DEVICE1_SIZE, \ 43 MT_DEVICE | MT_RW | MT_SECURE) 44 45 /* 46 * Need to be mapped with write permissions in order to set a new non-volatile 47 * counter value. 48 */ 49 #define MAP_DEVICE2 MAP_REGION_FLAT(DEVICE2_BASE, \ 50 DEVICE2_SIZE, \ 51 MT_DEVICE | MT_RW | MT_SECURE) 52 53 /* 54 * Table of memory regions for various BL stages to map using the MMU. 55 * This doesn't include Trusted SRAM as setup_page_tables() already takes care 56 * of mapping it. 57 * 58 * The flash needs to be mapped as writable in order to erase the FIP's Table of 59 * Contents in case of unrecoverable error (see plat_error_handler()). 60 */ 61 #ifdef IMAGE_BL1 62 const mmap_region_t plat_arm_mmap[] = { 63 ARM_MAP_SHARED_RAM, 64 V2M_MAP_FLASH0_RW, 65 V2M_MAP_IOFPGA, 66 MAP_DEVICE0, 67 MAP_DEVICE1, 68 #if TRUSTED_BOARD_BOOT 69 /* To access the Root of Trust Public Key registers. */ 70 MAP_DEVICE2, 71 /* Map DRAM to authenticate NS_BL2U image. */ 72 ARM_MAP_NS_DRAM1, 73 #endif 74 {0} 75 }; 76 #endif 77 #ifdef IMAGE_BL2 78 const mmap_region_t plat_arm_mmap[] = { 79 ARM_MAP_SHARED_RAM, 80 V2M_MAP_FLASH0_RW, 81 V2M_MAP_IOFPGA, 82 MAP_DEVICE0, 83 MAP_DEVICE1, 84 ARM_MAP_NS_DRAM1, 85 #ifdef AARCH64 86 ARM_MAP_DRAM2, 87 #endif 88 #ifdef SPD_tspd 89 ARM_MAP_TSP_SEC_MEM, 90 #endif 91 #if TRUSTED_BOARD_BOOT 92 /* To access the Root of Trust Public Key registers. */ 93 MAP_DEVICE2, 94 #if !BL2_AT_EL3 95 ARM_MAP_BL1_RW, 96 #endif 97 #endif /* TRUSTED_BOARD_BOOT */ 98 #if ENABLE_SPM && SPM_DEPRECATED 99 ARM_SP_IMAGE_MMAP, 100 #endif 101 #if ENABLE_SPM && !SPM_DEPRECATED 102 PLAT_MAP_SP_PACKAGE_MEM_RW, 103 #endif 104 #if ARM_BL31_IN_DRAM 105 ARM_MAP_BL31_SEC_DRAM, 106 #endif 107 #ifdef SPD_opteed 108 ARM_MAP_OPTEE_CORE_MEM, 109 ARM_OPTEE_PAGEABLE_LOAD_MEM, 110 #endif 111 {0} 112 }; 113 #endif 114 #ifdef IMAGE_BL2U 115 const mmap_region_t plat_arm_mmap[] = { 116 MAP_DEVICE0, 117 V2M_MAP_IOFPGA, 118 {0} 119 }; 120 #endif 121 #ifdef IMAGE_BL31 122 const mmap_region_t plat_arm_mmap[] = { 123 ARM_MAP_SHARED_RAM, 124 ARM_MAP_EL3_TZC_DRAM, 125 V2M_MAP_IOFPGA, 126 MAP_DEVICE0, 127 MAP_DEVICE1, 128 ARM_V2M_MAP_MEM_PROTECT, 129 #if ENABLE_SPM && SPM_DEPRECATED 130 ARM_SPM_BUF_EL3_MMAP, 131 #endif 132 #if ENABLE_SPM && !SPM_DEPRECATED 133 PLAT_MAP_SP_PACKAGE_MEM_RO, 134 #endif 135 {0} 136 }; 137 138 #if ENABLE_SPM && defined(IMAGE_BL31) && SPM_DEPRECATED 139 const mmap_region_t plat_arm_secure_partition_mmap[] = { 140 V2M_MAP_IOFPGA_EL0, /* for the UART */ 141 MAP_REGION_FLAT(DEVICE0_BASE, \ 142 DEVICE0_SIZE, \ 143 MT_DEVICE | MT_RO | MT_SECURE | MT_USER), 144 ARM_SP_IMAGE_MMAP, 145 ARM_SP_IMAGE_NS_BUF_MMAP, 146 ARM_SP_IMAGE_RW_MMAP, 147 ARM_SPM_BUF_EL0_MMAP, 148 {0} 149 }; 150 #endif 151 #endif 152 #ifdef IMAGE_BL32 153 const mmap_region_t plat_arm_mmap[] = { 154 #ifdef AARCH32 155 ARM_MAP_SHARED_RAM, 156 ARM_V2M_MAP_MEM_PROTECT, 157 #endif 158 V2M_MAP_IOFPGA, 159 MAP_DEVICE0, 160 MAP_DEVICE1, 161 {0} 162 }; 163 #endif 164 165 ARM_CASSERT_MMAP 166 167 #if FVP_INTERCONNECT_DRIVER != FVP_CCN 168 static const int fvp_cci400_map[] = { 169 PLAT_FVP_CCI400_CLUS0_SL_PORT, 170 PLAT_FVP_CCI400_CLUS1_SL_PORT, 171 }; 172 173 static const int fvp_cci5xx_map[] = { 174 PLAT_FVP_CCI5XX_CLUS0_SL_PORT, 175 PLAT_FVP_CCI5XX_CLUS1_SL_PORT, 176 }; 177 178 static unsigned int get_interconnect_master(void) 179 { 180 unsigned int master; 181 u_register_t mpidr; 182 183 mpidr = read_mpidr_el1(); 184 master = ((arm_config.flags & ARM_CONFIG_FVP_SHIFTED_AFF) != 0U) ? 185 MPIDR_AFFLVL2_VAL(mpidr) : MPIDR_AFFLVL1_VAL(mpidr); 186 187 assert(master < FVP_CLUSTER_COUNT); 188 return master; 189 } 190 #endif 191 192 #if ENABLE_SPM && defined(IMAGE_BL31) && SPM_DEPRECATED 193 /* 194 * Boot information passed to a secure partition during initialisation. Linear 195 * indices in MP information will be filled at runtime. 196 */ 197 static secure_partition_mp_info_t sp_mp_info[] = { 198 [0] = {0x80000000, 0}, 199 [1] = {0x80000001, 0}, 200 [2] = {0x80000002, 0}, 201 [3] = {0x80000003, 0}, 202 [4] = {0x80000100, 0}, 203 [5] = {0x80000101, 0}, 204 [6] = {0x80000102, 0}, 205 [7] = {0x80000103, 0}, 206 }; 207 208 const secure_partition_boot_info_t plat_arm_secure_partition_boot_info = { 209 .h.type = PARAM_SP_IMAGE_BOOT_INFO, 210 .h.version = VERSION_1, 211 .h.size = sizeof(secure_partition_boot_info_t), 212 .h.attr = 0, 213 .sp_mem_base = ARM_SP_IMAGE_BASE, 214 .sp_mem_limit = ARM_SP_IMAGE_LIMIT, 215 .sp_image_base = ARM_SP_IMAGE_BASE, 216 .sp_stack_base = PLAT_SP_IMAGE_STACK_BASE, 217 .sp_heap_base = ARM_SP_IMAGE_HEAP_BASE, 218 .sp_ns_comm_buf_base = PLAT_SP_IMAGE_NS_BUF_BASE, 219 .sp_shared_buf_base = PLAT_SPM_BUF_BASE, 220 .sp_image_size = ARM_SP_IMAGE_SIZE, 221 .sp_pcpu_stack_size = PLAT_SP_IMAGE_STACK_PCPU_SIZE, 222 .sp_heap_size = ARM_SP_IMAGE_HEAP_SIZE, 223 .sp_ns_comm_buf_size = PLAT_SP_IMAGE_NS_BUF_SIZE, 224 .sp_shared_buf_size = PLAT_SPM_BUF_SIZE, 225 .num_sp_mem_regions = ARM_SP_IMAGE_NUM_MEM_REGIONS, 226 .num_cpus = PLATFORM_CORE_COUNT, 227 .mp_info = &sp_mp_info[0], 228 }; 229 230 const struct mmap_region *plat_get_secure_partition_mmap(void *cookie) 231 { 232 return plat_arm_secure_partition_mmap; 233 } 234 235 const struct secure_partition_boot_info *plat_get_secure_partition_boot_info( 236 void *cookie) 237 { 238 return &plat_arm_secure_partition_boot_info; 239 } 240 #endif 241 242 /******************************************************************************* 243 * A single boot loader stack is expected to work on both the Foundation FVP 244 * models and the two flavours of the Base FVP models (AEMv8 & Cortex). The 245 * SYS_ID register provides a mechanism for detecting the differences between 246 * these platforms. This information is stored in a per-BL array to allow the 247 * code to take the correct path.Per BL platform configuration. 248 ******************************************************************************/ 249 void __init fvp_config_setup(void) 250 { 251 unsigned int rev, hbi, bld, arch, sys_id; 252 253 sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID); 254 rev = (sys_id >> V2M_SYS_ID_REV_SHIFT) & V2M_SYS_ID_REV_MASK; 255 hbi = (sys_id >> V2M_SYS_ID_HBI_SHIFT) & V2M_SYS_ID_HBI_MASK; 256 bld = (sys_id >> V2M_SYS_ID_BLD_SHIFT) & V2M_SYS_ID_BLD_MASK; 257 arch = (sys_id >> V2M_SYS_ID_ARCH_SHIFT) & V2M_SYS_ID_ARCH_MASK; 258 259 if (arch != ARCH_MODEL) { 260 ERROR("This firmware is for FVP models\n"); 261 panic(); 262 } 263 264 /* 265 * The build field in the SYS_ID tells which variant of the GIC 266 * memory is implemented by the model. 267 */ 268 switch (bld) { 269 case BLD_GIC_VE_MMAP: 270 ERROR("Legacy Versatile Express memory map for GIC peripheral" 271 " is not supported\n"); 272 panic(); 273 break; 274 case BLD_GIC_A53A57_MMAP: 275 break; 276 default: 277 ERROR("Unsupported board build %x\n", bld); 278 panic(); 279 } 280 281 /* 282 * The hbi field in the SYS_ID is 0x020 for the Base FVP & 0x010 283 * for the Foundation FVP. 284 */ 285 switch (hbi) { 286 case HBI_FOUNDATION_FVP: 287 arm_config.flags = 0; 288 289 /* 290 * Check for supported revisions of Foundation FVP 291 * Allow future revisions to run but emit warning diagnostic 292 */ 293 switch (rev) { 294 case REV_FOUNDATION_FVP_V2_0: 295 case REV_FOUNDATION_FVP_V2_1: 296 case REV_FOUNDATION_FVP_v9_1: 297 case REV_FOUNDATION_FVP_v9_6: 298 break; 299 default: 300 WARN("Unrecognized Foundation FVP revision %x\n", rev); 301 break; 302 } 303 break; 304 case HBI_BASE_FVP: 305 arm_config.flags |= (ARM_CONFIG_BASE_MMAP | ARM_CONFIG_HAS_TZC); 306 307 /* 308 * Check for supported revisions 309 * Allow future revisions to run but emit warning diagnostic 310 */ 311 switch (rev) { 312 case REV_BASE_FVP_V0: 313 arm_config.flags |= ARM_CONFIG_FVP_HAS_CCI400; 314 break; 315 case REV_BASE_FVP_REVC: 316 arm_config.flags |= (ARM_CONFIG_FVP_HAS_SMMUV3 | 317 ARM_CONFIG_FVP_HAS_CCI5XX); 318 break; 319 default: 320 WARN("Unrecognized Base FVP revision %x\n", rev); 321 break; 322 } 323 break; 324 default: 325 ERROR("Unsupported board HBI number 0x%x\n", hbi); 326 panic(); 327 } 328 329 /* 330 * We assume that the presence of MT bit, and therefore shifted 331 * affinities, is uniform across the platform: either all CPUs, or no 332 * CPUs implement it. 333 */ 334 if ((read_mpidr_el1() & MPIDR_MT_MASK) != 0U) 335 arm_config.flags |= ARM_CONFIG_FVP_SHIFTED_AFF; 336 } 337 338 339 void __init fvp_interconnect_init(void) 340 { 341 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 342 if (ccn_get_part0_id(PLAT_ARM_CCN_BASE) != CCN_502_PART0_ID) { 343 ERROR("Unrecognized CCN variant detected. Only CCN-502 is supported"); 344 panic(); 345 } 346 347 plat_arm_interconnect_init(); 348 #else 349 uintptr_t cci_base = 0U; 350 const int *cci_map = NULL; 351 unsigned int map_size = 0U; 352 353 /* Initialize the right interconnect */ 354 if ((arm_config.flags & ARM_CONFIG_FVP_HAS_CCI5XX) != 0U) { 355 cci_base = PLAT_FVP_CCI5XX_BASE; 356 cci_map = fvp_cci5xx_map; 357 map_size = ARRAY_SIZE(fvp_cci5xx_map); 358 } else if ((arm_config.flags & ARM_CONFIG_FVP_HAS_CCI400) != 0U) { 359 cci_base = PLAT_FVP_CCI400_BASE; 360 cci_map = fvp_cci400_map; 361 map_size = ARRAY_SIZE(fvp_cci400_map); 362 } else { 363 return; 364 } 365 366 assert(cci_base != 0U); 367 assert(cci_map != NULL); 368 cci_init(cci_base, cci_map, map_size); 369 #endif 370 } 371 372 void fvp_interconnect_enable(void) 373 { 374 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 375 plat_arm_interconnect_enter_coherency(); 376 #else 377 unsigned int master; 378 379 if ((arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 | 380 ARM_CONFIG_FVP_HAS_CCI5XX)) != 0U) { 381 master = get_interconnect_master(); 382 cci_enable_snoop_dvm_reqs(master); 383 } 384 #endif 385 } 386 387 void fvp_interconnect_disable(void) 388 { 389 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 390 plat_arm_interconnect_exit_coherency(); 391 #else 392 unsigned int master; 393 394 if ((arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 | 395 ARM_CONFIG_FVP_HAS_CCI5XX)) != 0U) { 396 master = get_interconnect_master(); 397 cci_disable_snoop_dvm_reqs(master); 398 } 399 #endif 400 } 401 402 #if TRUSTED_BOARD_BOOT 403 int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size) 404 { 405 assert(heap_addr != NULL); 406 assert(heap_size != NULL); 407 408 return arm_get_mbedtls_heap(heap_addr, heap_size); 409 } 410 #endif 411