1 /* 2 * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arm_config.h> 32 #include <arm_def.h> 33 #include <ccn.h> 34 #include <debug.h> 35 #include <gicv2.h> 36 #include <mmio.h> 37 #include <plat_arm.h> 38 #include <v2m_def.h> 39 #include "../fvp_def.h" 40 41 /* Defines for GIC Driver build time selection */ 42 #define FVP_GICV2 1 43 #define FVP_GICV3 2 44 #define FVP_GICV3_LEGACY 3 45 46 /******************************************************************************* 47 * arm_config holds the characteristics of the differences between the three FVP 48 * platforms (Base, A53_A57 & Foundation). It will be populated during cold boot 49 * at each boot stage by the primary before enabling the MMU (to allow 50 * interconnect configuration) & used thereafter. Each BL will have its own copy 51 * to allow independent operation. 52 ******************************************************************************/ 53 arm_config_t arm_config; 54 55 #define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \ 56 DEVICE0_SIZE, \ 57 MT_DEVICE | MT_RW | MT_SECURE) 58 59 #define MAP_DEVICE1 MAP_REGION_FLAT(DEVICE1_BASE, \ 60 DEVICE1_SIZE, \ 61 MT_DEVICE | MT_RW | MT_SECURE) 62 63 #define MAP_DEVICE2 MAP_REGION_FLAT(DEVICE2_BASE, \ 64 DEVICE2_SIZE, \ 65 MT_DEVICE | MT_RW | MT_SECURE) 66 67 68 /* 69 * Table of regions for various BL stages to map using the MMU. 70 * This doesn't include TZRAM as the 'mem_layout' argument passed to 71 * arm_configure_mmu_elx() will give the available subset of that, 72 */ 73 #if IMAGE_BL1 74 const mmap_region_t plat_arm_mmap[] = { 75 ARM_MAP_SHARED_RAM, 76 V2M_MAP_FLASH0_RW, 77 V2M_MAP_IOFPGA, 78 MAP_DEVICE0, 79 MAP_DEVICE1, 80 MAP_DEVICE2, 81 #if TRUSTED_BOARD_BOOT 82 ARM_MAP_NS_DRAM1, 83 #endif 84 {0} 85 }; 86 #endif 87 #if IMAGE_BL2 88 const mmap_region_t plat_arm_mmap[] = { 89 ARM_MAP_SHARED_RAM, 90 V2M_MAP_FLASH0_RW, 91 V2M_MAP_IOFPGA, 92 MAP_DEVICE0, 93 MAP_DEVICE1, 94 MAP_DEVICE2, 95 ARM_MAP_NS_DRAM1, 96 ARM_MAP_TSP_SEC_MEM, 97 #if ARM_BL31_IN_DRAM 98 ARM_MAP_BL31_SEC_DRAM, 99 #endif 100 {0} 101 }; 102 #endif 103 #if IMAGE_BL2U 104 const mmap_region_t plat_arm_mmap[] = { 105 MAP_DEVICE0, 106 V2M_MAP_IOFPGA, 107 {0} 108 }; 109 #endif 110 #if IMAGE_BL31 111 const mmap_region_t plat_arm_mmap[] = { 112 ARM_MAP_SHARED_RAM, 113 V2M_MAP_IOFPGA, 114 MAP_DEVICE0, 115 MAP_DEVICE1, 116 {0} 117 }; 118 #endif 119 #if IMAGE_BL32 120 const mmap_region_t plat_arm_mmap[] = { 121 V2M_MAP_IOFPGA, 122 MAP_DEVICE0, 123 MAP_DEVICE1, 124 {0} 125 }; 126 #endif 127 128 ARM_CASSERT_MMAP 129 130 131 /******************************************************************************* 132 * A single boot loader stack is expected to work on both the Foundation FVP 133 * models and the two flavours of the Base FVP models (AEMv8 & Cortex). The 134 * SYS_ID register provides a mechanism for detecting the differences between 135 * these platforms. This information is stored in a per-BL array to allow the 136 * code to take the correct path.Per BL platform configuration. 137 ******************************************************************************/ 138 void fvp_config_setup(void) 139 { 140 unsigned int rev, hbi, bld, arch, sys_id; 141 142 sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID); 143 rev = (sys_id >> V2M_SYS_ID_REV_SHIFT) & V2M_SYS_ID_REV_MASK; 144 hbi = (sys_id >> V2M_SYS_ID_HBI_SHIFT) & V2M_SYS_ID_HBI_MASK; 145 bld = (sys_id >> V2M_SYS_ID_BLD_SHIFT) & V2M_SYS_ID_BLD_MASK; 146 arch = (sys_id >> V2M_SYS_ID_ARCH_SHIFT) & V2M_SYS_ID_ARCH_MASK; 147 148 if (arch != ARCH_MODEL) { 149 ERROR("This firmware is for FVP models\n"); 150 panic(); 151 } 152 153 /* 154 * The build field in the SYS_ID tells which variant of the GIC 155 * memory is implemented by the model. 156 */ 157 switch (bld) { 158 case BLD_GIC_VE_MMAP: 159 ERROR("Legacy Versatile Express memory map for GIC peripheral" 160 " is not supported\n"); 161 panic(); 162 break; 163 case BLD_GIC_A53A57_MMAP: 164 break; 165 default: 166 ERROR("Unsupported board build %x\n", bld); 167 panic(); 168 } 169 170 /* 171 * The hbi field in the SYS_ID is 0x020 for the Base FVP & 0x010 172 * for the Foundation FVP. 173 */ 174 switch (hbi) { 175 case HBI_FOUNDATION_FVP: 176 arm_config.flags = 0; 177 178 /* 179 * Check for supported revisions of Foundation FVP 180 * Allow future revisions to run but emit warning diagnostic 181 */ 182 switch (rev) { 183 case REV_FOUNDATION_FVP_V2_0: 184 case REV_FOUNDATION_FVP_V2_1: 185 case REV_FOUNDATION_FVP_v9_1: 186 break; 187 default: 188 WARN("Unrecognized Foundation FVP revision %x\n", rev); 189 break; 190 } 191 break; 192 case HBI_BASE_FVP: 193 arm_config.flags |= ARM_CONFIG_BASE_MMAP | 194 ARM_CONFIG_HAS_INTERCONNECT | ARM_CONFIG_HAS_TZC; 195 196 /* 197 * Check for supported revisions 198 * Allow future revisions to run but emit warning diagnostic 199 */ 200 switch (rev) { 201 case REV_BASE_FVP_V0: 202 break; 203 default: 204 WARN("Unrecognized Base FVP revision %x\n", rev); 205 break; 206 } 207 break; 208 default: 209 ERROR("Unsupported board HBI number 0x%x\n", hbi); 210 panic(); 211 } 212 } 213 214 215 void fvp_interconnect_init(void) 216 { 217 if (arm_config.flags & ARM_CONFIG_HAS_INTERCONNECT) { 218 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 219 if (ccn_get_part0_id(PLAT_ARM_CCN_BASE) != CCN_502_PART0_ID) { 220 ERROR("Unrecognized CCN variant detected. Only CCN-502" 221 " is supported"); 222 panic(); 223 } 224 #endif 225 plat_arm_interconnect_init(); 226 } 227 } 228 229 void fvp_interconnect_enable(void) 230 { 231 if (arm_config.flags & ARM_CONFIG_HAS_INTERCONNECT) 232 plat_arm_interconnect_enter_coherency(); 233 } 234 235 void fvp_interconnect_disable(void) 236 { 237 if (arm_config.flags & ARM_CONFIG_HAS_INTERCONNECT) 238 plat_arm_interconnect_exit_coherency(); 239 } 240