1 /* 2 * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arm_config.h> 8 #include <arm_def.h> 9 #include <ccn.h> 10 #include <debug.h> 11 #include <gicv2.h> 12 #include <mmio.h> 13 #include <plat_arm.h> 14 #include <v2m_def.h> 15 #include "../fvp_def.h" 16 17 /* Defines for GIC Driver build time selection */ 18 #define FVP_GICV2 1 19 #define FVP_GICV3 2 20 #define FVP_GICV3_LEGACY 3 21 22 /******************************************************************************* 23 * arm_config holds the characteristics of the differences between the three FVP 24 * platforms (Base, A53_A57 & Foundation). It will be populated during cold boot 25 * at each boot stage by the primary before enabling the MMU (to allow 26 * interconnect configuration) & used thereafter. Each BL will have its own copy 27 * to allow independent operation. 28 ******************************************************************************/ 29 arm_config_t arm_config; 30 31 #define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \ 32 DEVICE0_SIZE, \ 33 MT_DEVICE | MT_RW | MT_SECURE) 34 35 #define MAP_DEVICE1 MAP_REGION_FLAT(DEVICE1_BASE, \ 36 DEVICE1_SIZE, \ 37 MT_DEVICE | MT_RW | MT_SECURE) 38 39 /* 40 * Need to be mapped with write permissions in order to set a new non-volatile 41 * counter value. 42 */ 43 #define MAP_DEVICE2 MAP_REGION_FLAT(DEVICE2_BASE, \ 44 DEVICE2_SIZE, \ 45 MT_DEVICE | MT_RW | MT_SECURE) 46 47 48 /* 49 * Table of memory regions for various BL stages to map using the MMU. 50 * This doesn't include Trusted SRAM as arm_setup_page_tables() already 51 * takes care of mapping it. 52 * 53 * The flash needs to be mapped as writable in order to erase the FIP's Table of 54 * Contents in case of unrecoverable error (see plat_error_handler()). 55 */ 56 #ifdef IMAGE_BL1 57 const mmap_region_t plat_arm_mmap[] = { 58 ARM_MAP_SHARED_RAM, 59 V2M_MAP_FLASH0_RW, 60 V2M_MAP_IOFPGA, 61 MAP_DEVICE0, 62 MAP_DEVICE1, 63 #if TRUSTED_BOARD_BOOT 64 /* To access the Root of Trust Public Key registers. */ 65 MAP_DEVICE2, 66 /* Map DRAM to authenticate NS_BL2U image. */ 67 ARM_MAP_NS_DRAM1, 68 #endif 69 {0} 70 }; 71 #endif 72 #ifdef IMAGE_BL2 73 const mmap_region_t plat_arm_mmap[] = { 74 ARM_MAP_SHARED_RAM, 75 V2M_MAP_FLASH0_RW, 76 V2M_MAP_IOFPGA, 77 MAP_DEVICE0, 78 MAP_DEVICE1, 79 ARM_MAP_NS_DRAM1, 80 ARM_MAP_TSP_SEC_MEM, 81 #if TRUSTED_BOARD_BOOT 82 /* To access the Root of Trust Public Key registers. */ 83 MAP_DEVICE2, 84 #endif 85 #if ARM_BL31_IN_DRAM 86 ARM_MAP_BL31_SEC_DRAM, 87 #endif 88 {0} 89 }; 90 #endif 91 #ifdef IMAGE_BL2U 92 const mmap_region_t plat_arm_mmap[] = { 93 MAP_DEVICE0, 94 V2M_MAP_IOFPGA, 95 {0} 96 }; 97 #endif 98 #ifdef IMAGE_BL31 99 const mmap_region_t plat_arm_mmap[] = { 100 ARM_MAP_SHARED_RAM, 101 V2M_MAP_IOFPGA, 102 MAP_DEVICE0, 103 MAP_DEVICE1, 104 {0} 105 }; 106 #endif 107 #ifdef IMAGE_BL32 108 const mmap_region_t plat_arm_mmap[] = { 109 #ifdef AARCH32 110 ARM_MAP_SHARED_RAM, 111 #endif 112 V2M_MAP_IOFPGA, 113 MAP_DEVICE0, 114 MAP_DEVICE1, 115 {0} 116 }; 117 #endif 118 119 ARM_CASSERT_MMAP 120 121 122 /******************************************************************************* 123 * A single boot loader stack is expected to work on both the Foundation FVP 124 * models and the two flavours of the Base FVP models (AEMv8 & Cortex). The 125 * SYS_ID register provides a mechanism for detecting the differences between 126 * these platforms. This information is stored in a per-BL array to allow the 127 * code to take the correct path.Per BL platform configuration. 128 ******************************************************************************/ 129 void fvp_config_setup(void) 130 { 131 unsigned int rev, hbi, bld, arch, sys_id; 132 133 sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID); 134 rev = (sys_id >> V2M_SYS_ID_REV_SHIFT) & V2M_SYS_ID_REV_MASK; 135 hbi = (sys_id >> V2M_SYS_ID_HBI_SHIFT) & V2M_SYS_ID_HBI_MASK; 136 bld = (sys_id >> V2M_SYS_ID_BLD_SHIFT) & V2M_SYS_ID_BLD_MASK; 137 arch = (sys_id >> V2M_SYS_ID_ARCH_SHIFT) & V2M_SYS_ID_ARCH_MASK; 138 139 if (arch != ARCH_MODEL) { 140 ERROR("This firmware is for FVP models\n"); 141 panic(); 142 } 143 144 /* 145 * The build field in the SYS_ID tells which variant of the GIC 146 * memory is implemented by the model. 147 */ 148 switch (bld) { 149 case BLD_GIC_VE_MMAP: 150 ERROR("Legacy Versatile Express memory map for GIC peripheral" 151 " is not supported\n"); 152 panic(); 153 break; 154 case BLD_GIC_A53A57_MMAP: 155 break; 156 default: 157 ERROR("Unsupported board build %x\n", bld); 158 panic(); 159 } 160 161 /* 162 * The hbi field in the SYS_ID is 0x020 for the Base FVP & 0x010 163 * for the Foundation FVP. 164 */ 165 switch (hbi) { 166 case HBI_FOUNDATION_FVP: 167 arm_config.flags = 0; 168 169 /* 170 * Check for supported revisions of Foundation FVP 171 * Allow future revisions to run but emit warning diagnostic 172 */ 173 switch (rev) { 174 case REV_FOUNDATION_FVP_V2_0: 175 case REV_FOUNDATION_FVP_V2_1: 176 case REV_FOUNDATION_FVP_v9_1: 177 case REV_FOUNDATION_FVP_v9_6: 178 break; 179 default: 180 WARN("Unrecognized Foundation FVP revision %x\n", rev); 181 break; 182 } 183 break; 184 case HBI_BASE_FVP: 185 arm_config.flags |= ARM_CONFIG_BASE_MMAP | 186 ARM_CONFIG_HAS_INTERCONNECT | ARM_CONFIG_HAS_TZC; 187 188 /* 189 * Check for supported revisions 190 * Allow future revisions to run but emit warning diagnostic 191 */ 192 switch (rev) { 193 case REV_BASE_FVP_V0: 194 break; 195 default: 196 WARN("Unrecognized Base FVP revision %x\n", rev); 197 break; 198 } 199 break; 200 default: 201 ERROR("Unsupported board HBI number 0x%x\n", hbi); 202 panic(); 203 } 204 } 205 206 207 void fvp_interconnect_init(void) 208 { 209 if (arm_config.flags & ARM_CONFIG_HAS_INTERCONNECT) { 210 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 211 if (ccn_get_part0_id(PLAT_ARM_CCN_BASE) != CCN_502_PART0_ID) { 212 ERROR("Unrecognized CCN variant detected. Only CCN-502" 213 " is supported"); 214 panic(); 215 } 216 #endif 217 plat_arm_interconnect_init(); 218 } 219 } 220 221 void fvp_interconnect_enable(void) 222 { 223 if (arm_config.flags & ARM_CONFIG_HAS_INTERCONNECT) 224 plat_arm_interconnect_enter_coherency(); 225 } 226 227 void fvp_interconnect_disable(void) 228 { 229 if (arm_config.flags & ARM_CONFIG_HAS_INTERCONNECT) 230 plat_arm_interconnect_exit_coherency(); 231 } 232