1 /* 2 * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <common/debug.h> 10 #include <drivers/arm/cci.h> 11 #include <drivers/arm/ccn.h> 12 #include <drivers/arm/gicv2.h> 13 #include <drivers/arm/sp804_delay_timer.h> 14 #include <drivers/generic_delay_timer.h> 15 #include <lib/mmio.h> 16 #include <lib/xlat_tables/xlat_tables_compat.h> 17 #include <plat/arm/common/arm_config.h> 18 #include <plat/arm/common/plat_arm.h> 19 #include <plat/common/platform.h> 20 #include <platform_def.h> 21 #include <services/spm_mm_partition.h> 22 23 #include "fvp_private.h" 24 25 /* Defines for GIC Driver build time selection */ 26 #define FVP_GICV2 1 27 #define FVP_GICV3 2 28 29 /******************************************************************************* 30 * arm_config holds the characteristics of the differences between the three FVP 31 * platforms (Base, A53_A57 & Foundation). It will be populated during cold boot 32 * at each boot stage by the primary before enabling the MMU (to allow 33 * interconnect configuration) & used thereafter. Each BL will have its own copy 34 * to allow independent operation. 35 ******************************************************************************/ 36 arm_config_t arm_config; 37 38 #define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \ 39 DEVICE0_SIZE, \ 40 MT_DEVICE | MT_RW | MT_SECURE) 41 42 #define MAP_DEVICE1 MAP_REGION_FLAT(DEVICE1_BASE, \ 43 DEVICE1_SIZE, \ 44 MT_DEVICE | MT_RW | MT_SECURE) 45 46 /* 47 * Need to be mapped with write permissions in order to set a new non-volatile 48 * counter value. 49 */ 50 #define MAP_DEVICE2 MAP_REGION_FLAT(DEVICE2_BASE, \ 51 DEVICE2_SIZE, \ 52 MT_DEVICE | MT_RW | MT_SECURE) 53 54 /* 55 * Table of memory regions for various BL stages to map using the MMU. 56 * This doesn't include Trusted SRAM as setup_page_tables() already takes care 57 * of mapping it. 58 * 59 * The flash needs to be mapped as writable in order to erase the FIP's Table of 60 * Contents in case of unrecoverable error (see plat_error_handler()). 61 */ 62 #ifdef IMAGE_BL1 63 const mmap_region_t plat_arm_mmap[] = { 64 ARM_MAP_SHARED_RAM, 65 V2M_MAP_FLASH0_RW, 66 V2M_MAP_IOFPGA, 67 MAP_DEVICE0, 68 MAP_DEVICE1, 69 #if TRUSTED_BOARD_BOOT 70 /* To access the Root of Trust Public Key registers. */ 71 MAP_DEVICE2, 72 /* Map DRAM to authenticate NS_BL2U image. */ 73 ARM_MAP_NS_DRAM1, 74 #endif 75 {0} 76 }; 77 #endif 78 #ifdef IMAGE_BL2 79 const mmap_region_t plat_arm_mmap[] = { 80 ARM_MAP_SHARED_RAM, 81 V2M_MAP_FLASH0_RW, 82 V2M_MAP_IOFPGA, 83 MAP_DEVICE0, 84 MAP_DEVICE1, 85 ARM_MAP_NS_DRAM1, 86 #ifdef __aarch64__ 87 ARM_MAP_DRAM2, 88 #endif 89 #if defined(SPD_spmd) 90 ARM_MAP_TRUSTED_DRAM, 91 #endif 92 #ifdef SPD_tspd 93 ARM_MAP_TSP_SEC_MEM, 94 #endif 95 #if TRUSTED_BOARD_BOOT 96 /* To access the Root of Trust Public Key registers. */ 97 MAP_DEVICE2, 98 #if !BL2_AT_EL3 99 ARM_MAP_BL1_RW, 100 #endif 101 #endif /* TRUSTED_BOARD_BOOT */ 102 #if SPM_MM 103 ARM_SP_IMAGE_MMAP, 104 #endif 105 #if ARM_BL31_IN_DRAM 106 ARM_MAP_BL31_SEC_DRAM, 107 #endif 108 #ifdef SPD_opteed 109 ARM_MAP_OPTEE_CORE_MEM, 110 ARM_OPTEE_PAGEABLE_LOAD_MEM, 111 #endif 112 {0} 113 }; 114 #endif 115 #ifdef IMAGE_BL2U 116 const mmap_region_t plat_arm_mmap[] = { 117 MAP_DEVICE0, 118 V2M_MAP_IOFPGA, 119 {0} 120 }; 121 #endif 122 #ifdef IMAGE_BL31 123 const mmap_region_t plat_arm_mmap[] = { 124 ARM_MAP_SHARED_RAM, 125 #if USE_DEBUGFS 126 /* Required by devfip, can be removed if devfip is not used */ 127 V2M_MAP_FLASH0_RW, 128 #endif /* USE_DEBUGFS */ 129 ARM_MAP_EL3_TZC_DRAM, 130 V2M_MAP_IOFPGA, 131 MAP_DEVICE0, 132 MAP_DEVICE1, 133 ARM_V2M_MAP_MEM_PROTECT, 134 #if SPM_MM 135 ARM_SPM_BUF_EL3_MMAP, 136 #endif 137 {0} 138 }; 139 140 #if defined(IMAGE_BL31) && SPM_MM 141 const mmap_region_t plat_arm_secure_partition_mmap[] = { 142 V2M_MAP_IOFPGA_EL0, /* for the UART */ 143 MAP_REGION_FLAT(DEVICE0_BASE, \ 144 DEVICE0_SIZE, \ 145 MT_DEVICE | MT_RO | MT_SECURE | MT_USER), 146 ARM_SP_IMAGE_MMAP, 147 ARM_SP_IMAGE_NS_BUF_MMAP, 148 ARM_SP_IMAGE_RW_MMAP, 149 ARM_SPM_BUF_EL0_MMAP, 150 {0} 151 }; 152 #endif 153 #endif 154 #ifdef IMAGE_BL32 155 const mmap_region_t plat_arm_mmap[] = { 156 #ifndef __aarch64__ 157 ARM_MAP_SHARED_RAM, 158 ARM_V2M_MAP_MEM_PROTECT, 159 #endif 160 V2M_MAP_IOFPGA, 161 MAP_DEVICE0, 162 MAP_DEVICE1, 163 {0} 164 }; 165 #endif 166 167 ARM_CASSERT_MMAP 168 169 #if FVP_INTERCONNECT_DRIVER != FVP_CCN 170 static const int fvp_cci400_map[] = { 171 PLAT_FVP_CCI400_CLUS0_SL_PORT, 172 PLAT_FVP_CCI400_CLUS1_SL_PORT, 173 }; 174 175 static const int fvp_cci5xx_map[] = { 176 PLAT_FVP_CCI5XX_CLUS0_SL_PORT, 177 PLAT_FVP_CCI5XX_CLUS1_SL_PORT, 178 }; 179 180 static unsigned int get_interconnect_master(void) 181 { 182 unsigned int master; 183 u_register_t mpidr; 184 185 mpidr = read_mpidr_el1(); 186 master = ((arm_config.flags & ARM_CONFIG_FVP_SHIFTED_AFF) != 0U) ? 187 MPIDR_AFFLVL2_VAL(mpidr) : MPIDR_AFFLVL1_VAL(mpidr); 188 189 assert(master < FVP_CLUSTER_COUNT); 190 return master; 191 } 192 #endif 193 194 #if defined(IMAGE_BL31) && SPM_MM 195 /* 196 * Boot information passed to a secure partition during initialisation. Linear 197 * indices in MP information will be filled at runtime. 198 */ 199 static spm_mm_mp_info_t sp_mp_info[] = { 200 [0] = {0x80000000, 0}, 201 [1] = {0x80000001, 0}, 202 [2] = {0x80000002, 0}, 203 [3] = {0x80000003, 0}, 204 [4] = {0x80000100, 0}, 205 [5] = {0x80000101, 0}, 206 [6] = {0x80000102, 0}, 207 [7] = {0x80000103, 0}, 208 }; 209 210 const spm_mm_boot_info_t plat_arm_secure_partition_boot_info = { 211 .h.type = PARAM_SP_IMAGE_BOOT_INFO, 212 .h.version = VERSION_1, 213 .h.size = sizeof(spm_mm_boot_info_t), 214 .h.attr = 0, 215 .sp_mem_base = ARM_SP_IMAGE_BASE, 216 .sp_mem_limit = ARM_SP_IMAGE_LIMIT, 217 .sp_image_base = ARM_SP_IMAGE_BASE, 218 .sp_stack_base = PLAT_SP_IMAGE_STACK_BASE, 219 .sp_heap_base = ARM_SP_IMAGE_HEAP_BASE, 220 .sp_ns_comm_buf_base = PLAT_SP_IMAGE_NS_BUF_BASE, 221 .sp_shared_buf_base = PLAT_SPM_BUF_BASE, 222 .sp_image_size = ARM_SP_IMAGE_SIZE, 223 .sp_pcpu_stack_size = PLAT_SP_IMAGE_STACK_PCPU_SIZE, 224 .sp_heap_size = ARM_SP_IMAGE_HEAP_SIZE, 225 .sp_ns_comm_buf_size = PLAT_SP_IMAGE_NS_BUF_SIZE, 226 .sp_shared_buf_size = PLAT_SPM_BUF_SIZE, 227 .num_sp_mem_regions = ARM_SP_IMAGE_NUM_MEM_REGIONS, 228 .num_cpus = PLATFORM_CORE_COUNT, 229 .mp_info = &sp_mp_info[0], 230 }; 231 232 const struct mmap_region *plat_get_secure_partition_mmap(void *cookie) 233 { 234 return plat_arm_secure_partition_mmap; 235 } 236 237 const struct spm_mm_boot_info *plat_get_secure_partition_boot_info( 238 void *cookie) 239 { 240 return &plat_arm_secure_partition_boot_info; 241 } 242 #endif 243 244 /******************************************************************************* 245 * A single boot loader stack is expected to work on both the Foundation FVP 246 * models and the two flavours of the Base FVP models (AEMv8 & Cortex). The 247 * SYS_ID register provides a mechanism for detecting the differences between 248 * these platforms. This information is stored in a per-BL array to allow the 249 * code to take the correct path.Per BL platform configuration. 250 ******************************************************************************/ 251 void __init fvp_config_setup(void) 252 { 253 unsigned int rev, hbi, bld, arch, sys_id; 254 255 sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID); 256 rev = (sys_id >> V2M_SYS_ID_REV_SHIFT) & V2M_SYS_ID_REV_MASK; 257 hbi = (sys_id >> V2M_SYS_ID_HBI_SHIFT) & V2M_SYS_ID_HBI_MASK; 258 bld = (sys_id >> V2M_SYS_ID_BLD_SHIFT) & V2M_SYS_ID_BLD_MASK; 259 arch = (sys_id >> V2M_SYS_ID_ARCH_SHIFT) & V2M_SYS_ID_ARCH_MASK; 260 261 if (arch != ARCH_MODEL) { 262 ERROR("This firmware is for FVP models\n"); 263 panic(); 264 } 265 266 /* 267 * The build field in the SYS_ID tells which variant of the GIC 268 * memory is implemented by the model. 269 */ 270 switch (bld) { 271 case BLD_GIC_VE_MMAP: 272 ERROR("Legacy Versatile Express memory map for GIC peripheral" 273 " is not supported\n"); 274 panic(); 275 break; 276 case BLD_GIC_A53A57_MMAP: 277 break; 278 default: 279 ERROR("Unsupported board build %x\n", bld); 280 panic(); 281 } 282 283 /* 284 * The hbi field in the SYS_ID is 0x020 for the Base FVP & 0x010 285 * for the Foundation FVP. 286 */ 287 switch (hbi) { 288 case HBI_FOUNDATION_FVP: 289 arm_config.flags = 0; 290 291 /* 292 * Check for supported revisions of Foundation FVP 293 * Allow future revisions to run but emit warning diagnostic 294 */ 295 switch (rev) { 296 case REV_FOUNDATION_FVP_V2_0: 297 case REV_FOUNDATION_FVP_V2_1: 298 case REV_FOUNDATION_FVP_v9_1: 299 case REV_FOUNDATION_FVP_v9_6: 300 break; 301 default: 302 WARN("Unrecognized Foundation FVP revision %x\n", rev); 303 break; 304 } 305 break; 306 case HBI_BASE_FVP: 307 arm_config.flags |= (ARM_CONFIG_BASE_MMAP | ARM_CONFIG_HAS_TZC); 308 309 /* 310 * Check for supported revisions 311 * Allow future revisions to run but emit warning diagnostic 312 */ 313 switch (rev) { 314 case REV_BASE_FVP_V0: 315 arm_config.flags |= ARM_CONFIG_FVP_HAS_CCI400; 316 break; 317 case REV_BASE_FVP_REVC: 318 arm_config.flags |= (ARM_CONFIG_FVP_HAS_SMMUV3 | 319 ARM_CONFIG_FVP_HAS_CCI5XX); 320 break; 321 default: 322 WARN("Unrecognized Base FVP revision %x\n", rev); 323 break; 324 } 325 break; 326 default: 327 ERROR("Unsupported board HBI number 0x%x\n", hbi); 328 panic(); 329 } 330 331 /* 332 * We assume that the presence of MT bit, and therefore shifted 333 * affinities, is uniform across the platform: either all CPUs, or no 334 * CPUs implement it. 335 */ 336 if ((read_mpidr_el1() & MPIDR_MT_MASK) != 0U) 337 arm_config.flags |= ARM_CONFIG_FVP_SHIFTED_AFF; 338 } 339 340 341 void __init fvp_interconnect_init(void) 342 { 343 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 344 if (ccn_get_part0_id(PLAT_ARM_CCN_BASE) != CCN_502_PART0_ID) { 345 ERROR("Unrecognized CCN variant detected. Only CCN-502 is supported"); 346 panic(); 347 } 348 349 plat_arm_interconnect_init(); 350 #else 351 uintptr_t cci_base = 0U; 352 const int *cci_map = NULL; 353 unsigned int map_size = 0U; 354 355 /* Initialize the right interconnect */ 356 if ((arm_config.flags & ARM_CONFIG_FVP_HAS_CCI5XX) != 0U) { 357 cci_base = PLAT_FVP_CCI5XX_BASE; 358 cci_map = fvp_cci5xx_map; 359 map_size = ARRAY_SIZE(fvp_cci5xx_map); 360 } else if ((arm_config.flags & ARM_CONFIG_FVP_HAS_CCI400) != 0U) { 361 cci_base = PLAT_FVP_CCI400_BASE; 362 cci_map = fvp_cci400_map; 363 map_size = ARRAY_SIZE(fvp_cci400_map); 364 } else { 365 return; 366 } 367 368 assert(cci_base != 0U); 369 assert(cci_map != NULL); 370 cci_init(cci_base, cci_map, map_size); 371 #endif 372 } 373 374 void fvp_interconnect_enable(void) 375 { 376 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 377 plat_arm_interconnect_enter_coherency(); 378 #else 379 unsigned int master; 380 381 if ((arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 | 382 ARM_CONFIG_FVP_HAS_CCI5XX)) != 0U) { 383 master = get_interconnect_master(); 384 cci_enable_snoop_dvm_reqs(master); 385 } 386 #endif 387 } 388 389 void fvp_interconnect_disable(void) 390 { 391 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 392 plat_arm_interconnect_exit_coherency(); 393 #else 394 unsigned int master; 395 396 if ((arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 | 397 ARM_CONFIG_FVP_HAS_CCI5XX)) != 0U) { 398 master = get_interconnect_master(); 399 cci_disable_snoop_dvm_reqs(master); 400 } 401 #endif 402 } 403 404 #if TRUSTED_BOARD_BOOT 405 int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size) 406 { 407 assert(heap_addr != NULL); 408 assert(heap_size != NULL); 409 410 return arm_get_mbedtls_heap(heap_addr, heap_size); 411 } 412 #endif 413 414 void fvp_timer_init(void) 415 { 416 #if FVP_USE_SP804_TIMER 417 /* Enable the clock override for SP804 timer 0, which means that no 418 * clock dividers are applied and the raw (35MHz) clock will be used. 419 */ 420 mmio_write_32(V2M_SP810_BASE, FVP_SP810_CTRL_TIM0_OV); 421 422 /* Initialize delay timer driver using SP804 dual timer 0 */ 423 sp804_timer_init(V2M_SP804_TIMER0_BASE, 424 SP804_TIMER_CLKMULT, SP804_TIMER_CLKDIV); 425 #else 426 generic_delay_timer_init(); 427 428 /* Enable System level generic timer */ 429 mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF, 430 CNTCR_FCREQ(0U) | CNTCR_EN); 431 #endif /* FVP_USE_SP804_TIMER */ 432 } 433