1 /* 2 * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arm_config.h> 32 #include <arm_def.h> 33 #include <debug.h> 34 #include <gicv2.h> 35 #include <mmio.h> 36 #include <plat_arm.h> 37 #include <v2m_def.h> 38 #include "../fvp_def.h" 39 40 /* Defines for GIC Driver build time selection */ 41 #define FVP_GICV2 1 42 #define FVP_GICV3 2 43 #define FVP_GICV3_LEGACY 3 44 45 /******************************************************************************* 46 * arm_config holds the characteristics of the differences between the three FVP 47 * platforms (Base, A53_A57 & Foundation). It will be populated during cold boot 48 * at each boot stage by the primary before enabling the MMU (to allow 49 * interconnect configuration) & used thereafter. Each BL will have its own copy 50 * to allow independent operation. 51 ******************************************************************************/ 52 arm_config_t arm_config; 53 54 #define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \ 55 DEVICE0_SIZE, \ 56 MT_DEVICE | MT_RW | MT_SECURE) 57 58 #define MAP_DEVICE1 MAP_REGION_FLAT(DEVICE1_BASE, \ 59 DEVICE1_SIZE, \ 60 MT_DEVICE | MT_RW | MT_SECURE) 61 62 #define MAP_DEVICE2 MAP_REGION_FLAT(DEVICE2_BASE, \ 63 DEVICE2_SIZE, \ 64 MT_DEVICE | MT_RO | MT_SECURE) 65 66 67 /* 68 * Table of regions for various BL stages to map using the MMU. 69 * This doesn't include TZRAM as the 'mem_layout' argument passed to 70 * arm_configure_mmu_elx() will give the available subset of that, 71 */ 72 #if IMAGE_BL1 73 const mmap_region_t plat_arm_mmap[] = { 74 ARM_MAP_SHARED_RAM, 75 V2M_MAP_FLASH0_RW, 76 V2M_MAP_IOFPGA, 77 MAP_DEVICE0, 78 MAP_DEVICE1, 79 MAP_DEVICE2, 80 #if TRUSTED_BOARD_BOOT 81 ARM_MAP_NS_DRAM1, 82 #endif 83 {0} 84 }; 85 #endif 86 #if IMAGE_BL2 87 const mmap_region_t plat_arm_mmap[] = { 88 ARM_MAP_SHARED_RAM, 89 V2M_MAP_FLASH0_RW, 90 V2M_MAP_IOFPGA, 91 MAP_DEVICE0, 92 MAP_DEVICE1, 93 MAP_DEVICE2, 94 ARM_MAP_NS_DRAM1, 95 ARM_MAP_TSP_SEC_MEM, 96 #if ARM_BL31_IN_DRAM 97 ARM_MAP_BL31_SEC_DRAM, 98 #endif 99 {0} 100 }; 101 #endif 102 #if IMAGE_BL2U 103 const mmap_region_t plat_arm_mmap[] = { 104 MAP_DEVICE0, 105 V2M_MAP_IOFPGA, 106 {0} 107 }; 108 #endif 109 #if IMAGE_BL31 110 const mmap_region_t plat_arm_mmap[] = { 111 ARM_MAP_SHARED_RAM, 112 V2M_MAP_IOFPGA, 113 MAP_DEVICE0, 114 MAP_DEVICE1, 115 {0} 116 }; 117 #endif 118 #if IMAGE_BL32 119 const mmap_region_t plat_arm_mmap[] = { 120 V2M_MAP_IOFPGA, 121 MAP_DEVICE0, 122 MAP_DEVICE1, 123 {0} 124 }; 125 #endif 126 127 ARM_CASSERT_MMAP 128 129 130 /******************************************************************************* 131 * A single boot loader stack is expected to work on both the Foundation FVP 132 * models and the two flavours of the Base FVP models (AEMv8 & Cortex). The 133 * SYS_ID register provides a mechanism for detecting the differences between 134 * these platforms. This information is stored in a per-BL array to allow the 135 * code to take the correct path.Per BL platform configuration. 136 ******************************************************************************/ 137 void fvp_config_setup(void) 138 { 139 unsigned int rev, hbi, bld, arch, sys_id; 140 141 sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID); 142 rev = (sys_id >> V2M_SYS_ID_REV_SHIFT) & V2M_SYS_ID_REV_MASK; 143 hbi = (sys_id >> V2M_SYS_ID_HBI_SHIFT) & V2M_SYS_ID_HBI_MASK; 144 bld = (sys_id >> V2M_SYS_ID_BLD_SHIFT) & V2M_SYS_ID_BLD_MASK; 145 arch = (sys_id >> V2M_SYS_ID_ARCH_SHIFT) & V2M_SYS_ID_ARCH_MASK; 146 147 if (arch != ARCH_MODEL) { 148 ERROR("This firmware is for FVP models\n"); 149 panic(); 150 } 151 152 /* 153 * The build field in the SYS_ID tells which variant of the GIC 154 * memory is implemented by the model. 155 */ 156 switch (bld) { 157 case BLD_GIC_VE_MMAP: 158 ERROR("Legacy Versatile Express memory map for GIC peripheral" 159 " is not supported\n"); 160 panic(); 161 break; 162 case BLD_GIC_A53A57_MMAP: 163 break; 164 default: 165 ERROR("Unsupported board build %x\n", bld); 166 panic(); 167 } 168 169 /* 170 * The hbi field in the SYS_ID is 0x020 for the Base FVP & 0x010 171 * for the Foundation FVP. 172 */ 173 switch (hbi) { 174 case HBI_FOUNDATION_FVP: 175 arm_config.flags = 0; 176 177 /* 178 * Check for supported revisions of Foundation FVP 179 * Allow future revisions to run but emit warning diagnostic 180 */ 181 switch (rev) { 182 case REV_FOUNDATION_FVP_V2_0: 183 case REV_FOUNDATION_FVP_V2_1: 184 case REV_FOUNDATION_FVP_v9_1: 185 break; 186 default: 187 WARN("Unrecognized Foundation FVP revision %x\n", rev); 188 break; 189 } 190 break; 191 case HBI_BASE_FVP: 192 arm_config.flags |= ARM_CONFIG_BASE_MMAP | 193 ARM_CONFIG_HAS_INTERCONNECT | ARM_CONFIG_HAS_TZC; 194 195 /* 196 * Check for supported revisions 197 * Allow future revisions to run but emit warning diagnostic 198 */ 199 switch (rev) { 200 case REV_BASE_FVP_V0: 201 break; 202 default: 203 WARN("Unrecognized Base FVP revision %x\n", rev); 204 break; 205 } 206 break; 207 default: 208 ERROR("Unsupported board HBI number 0x%x\n", hbi); 209 panic(); 210 } 211 } 212 213 214 void fvp_interconnect_init(void) 215 { 216 if (arm_config.flags & ARM_CONFIG_HAS_INTERCONNECT) 217 plat_arm_interconnect_init(); 218 } 219 220 void fvp_interconnect_enable(void) 221 { 222 if (arm_config.flags & ARM_CONFIG_HAS_INTERCONNECT) 223 plat_arm_interconnect_enter_coherency(); 224 } 225 226 void fvp_interconnect_disable(void) 227 { 228 if (arm_config.flags & ARM_CONFIG_HAS_INTERCONNECT) 229 plat_arm_interconnect_exit_coherency(); 230 } 231