1 /* 2 * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <common/debug.h> 10 #include <drivers/arm/cci.h> 11 #include <drivers/arm/ccn.h> 12 #include <drivers/arm/gicv2.h> 13 #include <drivers/arm/sp804_delay_timer.h> 14 #include <drivers/generic_delay_timer.h> 15 #include <lib/mmio.h> 16 #include <lib/xlat_tables/xlat_tables_compat.h> 17 #include <plat/arm/common/arm_config.h> 18 #include <plat/arm/common/plat_arm.h> 19 #include <plat/common/platform.h> 20 #include <platform_def.h> 21 #include <services/secure_partition.h> 22 23 #include "fvp_private.h" 24 25 /* Defines for GIC Driver build time selection */ 26 #define FVP_GICV2 1 27 #define FVP_GICV3 2 28 29 /******************************************************************************* 30 * arm_config holds the characteristics of the differences between the three FVP 31 * platforms (Base, A53_A57 & Foundation). It will be populated during cold boot 32 * at each boot stage by the primary before enabling the MMU (to allow 33 * interconnect configuration) & used thereafter. Each BL will have its own copy 34 * to allow independent operation. 35 ******************************************************************************/ 36 arm_config_t arm_config; 37 38 #define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \ 39 DEVICE0_SIZE, \ 40 MT_DEVICE | MT_RW | MT_SECURE) 41 42 #define MAP_DEVICE1 MAP_REGION_FLAT(DEVICE1_BASE, \ 43 DEVICE1_SIZE, \ 44 MT_DEVICE | MT_RW | MT_SECURE) 45 46 /* 47 * Need to be mapped with write permissions in order to set a new non-volatile 48 * counter value. 49 */ 50 #define MAP_DEVICE2 MAP_REGION_FLAT(DEVICE2_BASE, \ 51 DEVICE2_SIZE, \ 52 MT_DEVICE | MT_RW | MT_SECURE) 53 54 /* 55 * Table of memory regions for various BL stages to map using the MMU. 56 * This doesn't include Trusted SRAM as setup_page_tables() already takes care 57 * of mapping it. 58 * 59 * The flash needs to be mapped as writable in order to erase the FIP's Table of 60 * Contents in case of unrecoverable error (see plat_error_handler()). 61 */ 62 #ifdef IMAGE_BL1 63 const mmap_region_t plat_arm_mmap[] = { 64 ARM_MAP_SHARED_RAM, 65 V2M_MAP_FLASH0_RW, 66 V2M_MAP_IOFPGA, 67 MAP_DEVICE0, 68 MAP_DEVICE1, 69 #if TRUSTED_BOARD_BOOT 70 /* To access the Root of Trust Public Key registers. */ 71 MAP_DEVICE2, 72 /* Map DRAM to authenticate NS_BL2U image. */ 73 ARM_MAP_NS_DRAM1, 74 #endif 75 {0} 76 }; 77 #endif 78 #ifdef IMAGE_BL2 79 const mmap_region_t plat_arm_mmap[] = { 80 ARM_MAP_SHARED_RAM, 81 V2M_MAP_FLASH0_RW, 82 V2M_MAP_IOFPGA, 83 MAP_DEVICE0, 84 MAP_DEVICE1, 85 ARM_MAP_NS_DRAM1, 86 #ifdef __aarch64__ 87 ARM_MAP_DRAM2, 88 #endif 89 #ifdef SPD_tspd 90 ARM_MAP_TSP_SEC_MEM, 91 #endif 92 #if TRUSTED_BOARD_BOOT 93 /* To access the Root of Trust Public Key registers. */ 94 MAP_DEVICE2, 95 #if !BL2_AT_EL3 96 ARM_MAP_BL1_RW, 97 #endif 98 #endif /* TRUSTED_BOARD_BOOT */ 99 #if ENABLE_SPM && SPM_MM 100 ARM_SP_IMAGE_MMAP, 101 #endif 102 #if ENABLE_SPM && !SPM_MM 103 PLAT_MAP_SP_PACKAGE_MEM_RW, 104 #endif 105 #if ARM_BL31_IN_DRAM 106 ARM_MAP_BL31_SEC_DRAM, 107 #endif 108 #ifdef SPD_opteed 109 ARM_MAP_OPTEE_CORE_MEM, 110 ARM_OPTEE_PAGEABLE_LOAD_MEM, 111 #endif 112 {0} 113 }; 114 #endif 115 #ifdef IMAGE_BL2U 116 const mmap_region_t plat_arm_mmap[] = { 117 MAP_DEVICE0, 118 V2M_MAP_IOFPGA, 119 {0} 120 }; 121 #endif 122 #ifdef IMAGE_BL31 123 const mmap_region_t plat_arm_mmap[] = { 124 ARM_MAP_SHARED_RAM, 125 ARM_MAP_EL3_TZC_DRAM, 126 V2M_MAP_IOFPGA, 127 MAP_DEVICE0, 128 MAP_DEVICE1, 129 ARM_V2M_MAP_MEM_PROTECT, 130 #if ENABLE_SPM && SPM_MM 131 ARM_SPM_BUF_EL3_MMAP, 132 #endif 133 #if ENABLE_SPM && !SPM_MM 134 PLAT_MAP_SP_PACKAGE_MEM_RO, 135 #endif 136 {0} 137 }; 138 139 #if ENABLE_SPM && defined(IMAGE_BL31) && SPM_MM 140 const mmap_region_t plat_arm_secure_partition_mmap[] = { 141 V2M_MAP_IOFPGA_EL0, /* for the UART */ 142 MAP_REGION_FLAT(DEVICE0_BASE, \ 143 DEVICE0_SIZE, \ 144 MT_DEVICE | MT_RO | MT_SECURE | MT_USER), 145 ARM_SP_IMAGE_MMAP, 146 ARM_SP_IMAGE_NS_BUF_MMAP, 147 ARM_SP_IMAGE_RW_MMAP, 148 ARM_SPM_BUF_EL0_MMAP, 149 {0} 150 }; 151 #endif 152 #endif 153 #ifdef IMAGE_BL32 154 const mmap_region_t plat_arm_mmap[] = { 155 #ifndef __aarch64__ 156 ARM_MAP_SHARED_RAM, 157 ARM_V2M_MAP_MEM_PROTECT, 158 #endif 159 V2M_MAP_IOFPGA, 160 MAP_DEVICE0, 161 MAP_DEVICE1, 162 {0} 163 }; 164 #endif 165 166 ARM_CASSERT_MMAP 167 168 #if FVP_INTERCONNECT_DRIVER != FVP_CCN 169 static const int fvp_cci400_map[] = { 170 PLAT_FVP_CCI400_CLUS0_SL_PORT, 171 PLAT_FVP_CCI400_CLUS1_SL_PORT, 172 }; 173 174 static const int fvp_cci5xx_map[] = { 175 PLAT_FVP_CCI5XX_CLUS0_SL_PORT, 176 PLAT_FVP_CCI5XX_CLUS1_SL_PORT, 177 }; 178 179 static unsigned int get_interconnect_master(void) 180 { 181 unsigned int master; 182 u_register_t mpidr; 183 184 mpidr = read_mpidr_el1(); 185 master = ((arm_config.flags & ARM_CONFIG_FVP_SHIFTED_AFF) != 0U) ? 186 MPIDR_AFFLVL2_VAL(mpidr) : MPIDR_AFFLVL1_VAL(mpidr); 187 188 assert(master < FVP_CLUSTER_COUNT); 189 return master; 190 } 191 #endif 192 193 #if ENABLE_SPM && defined(IMAGE_BL31) && SPM_MM 194 /* 195 * Boot information passed to a secure partition during initialisation. Linear 196 * indices in MP information will be filled at runtime. 197 */ 198 static secure_partition_mp_info_t sp_mp_info[] = { 199 [0] = {0x80000000, 0}, 200 [1] = {0x80000001, 0}, 201 [2] = {0x80000002, 0}, 202 [3] = {0x80000003, 0}, 203 [4] = {0x80000100, 0}, 204 [5] = {0x80000101, 0}, 205 [6] = {0x80000102, 0}, 206 [7] = {0x80000103, 0}, 207 }; 208 209 const secure_partition_boot_info_t plat_arm_secure_partition_boot_info = { 210 .h.type = PARAM_SP_IMAGE_BOOT_INFO, 211 .h.version = VERSION_1, 212 .h.size = sizeof(secure_partition_boot_info_t), 213 .h.attr = 0, 214 .sp_mem_base = ARM_SP_IMAGE_BASE, 215 .sp_mem_limit = ARM_SP_IMAGE_LIMIT, 216 .sp_image_base = ARM_SP_IMAGE_BASE, 217 .sp_stack_base = PLAT_SP_IMAGE_STACK_BASE, 218 .sp_heap_base = ARM_SP_IMAGE_HEAP_BASE, 219 .sp_ns_comm_buf_base = PLAT_SP_IMAGE_NS_BUF_BASE, 220 .sp_shared_buf_base = PLAT_SPM_BUF_BASE, 221 .sp_image_size = ARM_SP_IMAGE_SIZE, 222 .sp_pcpu_stack_size = PLAT_SP_IMAGE_STACK_PCPU_SIZE, 223 .sp_heap_size = ARM_SP_IMAGE_HEAP_SIZE, 224 .sp_ns_comm_buf_size = PLAT_SP_IMAGE_NS_BUF_SIZE, 225 .sp_shared_buf_size = PLAT_SPM_BUF_SIZE, 226 .num_sp_mem_regions = ARM_SP_IMAGE_NUM_MEM_REGIONS, 227 .num_cpus = PLATFORM_CORE_COUNT, 228 .mp_info = &sp_mp_info[0], 229 }; 230 231 const struct mmap_region *plat_get_secure_partition_mmap(void *cookie) 232 { 233 return plat_arm_secure_partition_mmap; 234 } 235 236 const struct secure_partition_boot_info *plat_get_secure_partition_boot_info( 237 void *cookie) 238 { 239 return &plat_arm_secure_partition_boot_info; 240 } 241 #endif 242 243 /******************************************************************************* 244 * A single boot loader stack is expected to work on both the Foundation FVP 245 * models and the two flavours of the Base FVP models (AEMv8 & Cortex). The 246 * SYS_ID register provides a mechanism for detecting the differences between 247 * these platforms. This information is stored in a per-BL array to allow the 248 * code to take the correct path.Per BL platform configuration. 249 ******************************************************************************/ 250 void __init fvp_config_setup(void) 251 { 252 unsigned int rev, hbi, bld, arch, sys_id; 253 254 sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID); 255 rev = (sys_id >> V2M_SYS_ID_REV_SHIFT) & V2M_SYS_ID_REV_MASK; 256 hbi = (sys_id >> V2M_SYS_ID_HBI_SHIFT) & V2M_SYS_ID_HBI_MASK; 257 bld = (sys_id >> V2M_SYS_ID_BLD_SHIFT) & V2M_SYS_ID_BLD_MASK; 258 arch = (sys_id >> V2M_SYS_ID_ARCH_SHIFT) & V2M_SYS_ID_ARCH_MASK; 259 260 if (arch != ARCH_MODEL) { 261 ERROR("This firmware is for FVP models\n"); 262 panic(); 263 } 264 265 /* 266 * The build field in the SYS_ID tells which variant of the GIC 267 * memory is implemented by the model. 268 */ 269 switch (bld) { 270 case BLD_GIC_VE_MMAP: 271 ERROR("Legacy Versatile Express memory map for GIC peripheral" 272 " is not supported\n"); 273 panic(); 274 break; 275 case BLD_GIC_A53A57_MMAP: 276 break; 277 default: 278 ERROR("Unsupported board build %x\n", bld); 279 panic(); 280 } 281 282 /* 283 * The hbi field in the SYS_ID is 0x020 for the Base FVP & 0x010 284 * for the Foundation FVP. 285 */ 286 switch (hbi) { 287 case HBI_FOUNDATION_FVP: 288 arm_config.flags = 0; 289 290 /* 291 * Check for supported revisions of Foundation FVP 292 * Allow future revisions to run but emit warning diagnostic 293 */ 294 switch (rev) { 295 case REV_FOUNDATION_FVP_V2_0: 296 case REV_FOUNDATION_FVP_V2_1: 297 case REV_FOUNDATION_FVP_v9_1: 298 case REV_FOUNDATION_FVP_v9_6: 299 break; 300 default: 301 WARN("Unrecognized Foundation FVP revision %x\n", rev); 302 break; 303 } 304 break; 305 case HBI_BASE_FVP: 306 arm_config.flags |= (ARM_CONFIG_BASE_MMAP | ARM_CONFIG_HAS_TZC); 307 308 /* 309 * Check for supported revisions 310 * Allow future revisions to run but emit warning diagnostic 311 */ 312 switch (rev) { 313 case REV_BASE_FVP_V0: 314 arm_config.flags |= ARM_CONFIG_FVP_HAS_CCI400; 315 break; 316 case REV_BASE_FVP_REVC: 317 arm_config.flags |= (ARM_CONFIG_FVP_HAS_SMMUV3 | 318 ARM_CONFIG_FVP_HAS_CCI5XX); 319 break; 320 default: 321 WARN("Unrecognized Base FVP revision %x\n", rev); 322 break; 323 } 324 break; 325 default: 326 ERROR("Unsupported board HBI number 0x%x\n", hbi); 327 panic(); 328 } 329 330 /* 331 * We assume that the presence of MT bit, and therefore shifted 332 * affinities, is uniform across the platform: either all CPUs, or no 333 * CPUs implement it. 334 */ 335 if ((read_mpidr_el1() & MPIDR_MT_MASK) != 0U) 336 arm_config.flags |= ARM_CONFIG_FVP_SHIFTED_AFF; 337 } 338 339 340 void __init fvp_interconnect_init(void) 341 { 342 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 343 if (ccn_get_part0_id(PLAT_ARM_CCN_BASE) != CCN_502_PART0_ID) { 344 ERROR("Unrecognized CCN variant detected. Only CCN-502 is supported"); 345 panic(); 346 } 347 348 plat_arm_interconnect_init(); 349 #else 350 uintptr_t cci_base = 0U; 351 const int *cci_map = NULL; 352 unsigned int map_size = 0U; 353 354 /* Initialize the right interconnect */ 355 if ((arm_config.flags & ARM_CONFIG_FVP_HAS_CCI5XX) != 0U) { 356 cci_base = PLAT_FVP_CCI5XX_BASE; 357 cci_map = fvp_cci5xx_map; 358 map_size = ARRAY_SIZE(fvp_cci5xx_map); 359 } else if ((arm_config.flags & ARM_CONFIG_FVP_HAS_CCI400) != 0U) { 360 cci_base = PLAT_FVP_CCI400_BASE; 361 cci_map = fvp_cci400_map; 362 map_size = ARRAY_SIZE(fvp_cci400_map); 363 } else { 364 return; 365 } 366 367 assert(cci_base != 0U); 368 assert(cci_map != NULL); 369 cci_init(cci_base, cci_map, map_size); 370 #endif 371 } 372 373 void fvp_interconnect_enable(void) 374 { 375 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 376 plat_arm_interconnect_enter_coherency(); 377 #else 378 unsigned int master; 379 380 if ((arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 | 381 ARM_CONFIG_FVP_HAS_CCI5XX)) != 0U) { 382 master = get_interconnect_master(); 383 cci_enable_snoop_dvm_reqs(master); 384 } 385 #endif 386 } 387 388 void fvp_interconnect_disable(void) 389 { 390 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 391 plat_arm_interconnect_exit_coherency(); 392 #else 393 unsigned int master; 394 395 if ((arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 | 396 ARM_CONFIG_FVP_HAS_CCI5XX)) != 0U) { 397 master = get_interconnect_master(); 398 cci_disable_snoop_dvm_reqs(master); 399 } 400 #endif 401 } 402 403 #if TRUSTED_BOARD_BOOT 404 int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size) 405 { 406 assert(heap_addr != NULL); 407 assert(heap_size != NULL); 408 409 return arm_get_mbedtls_heap(heap_addr, heap_size); 410 } 411 #endif 412 413 void fvp_timer_init(void) 414 { 415 #if FVP_USE_SP804_TIMER 416 /* Enable the clock override for SP804 timer 0, which means that no 417 * clock dividers are applied and the raw (35MHz) clock will be used. 418 */ 419 mmio_write_32(V2M_SP810_BASE, FVP_SP810_CTRL_TIM0_OV); 420 421 /* Initialize delay timer driver using SP804 dual timer 0 */ 422 sp804_timer_init(V2M_SP804_TIMER0_BASE, 423 SP804_TIMER_CLKMULT, SP804_TIMER_CLKDIV); 424 #else 425 generic_delay_timer_init(); 426 427 /* Enable System level generic timer */ 428 mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF, 429 CNTCR_FCREQ(0U) | CNTCR_EN); 430 #endif /* FVP_USE_SP804_TIMER */ 431 } 432